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In the past several decades, the NAND flash memory encounters a great scaling of floating gate cell [1]. With the scaling of floating gate cell below 2X node, challenges related to the physical and electrical issues emerge. In the cell contact formation, dimension shrink and bowing profile related to the high aspect ratio seems to be difficult to overcome. The gap between lithography tools and cell...
Pulsed capacitively coupled plasmas (CCP) was applied to self-aligned-via (SAV) based all-in-one (AIO) etching process. Effects of bias and synchronous pulsed plasmas on the AIO etching process were analyzed to improve the reliability and reduce the RC delay in back-end-of-line (BEOL) copper interconnect system. For steps of hard-mask open and partial via etch, synchronous pulsed plasmas were applied...
As logic technology keeps shrinking to 28nm and below, Ultra Low-£ (ULK) dielectric film is widely used in BEoL (Back End of Line) to improve RC performance. To reduce k value damage, weaker post dry-etch cleaning is used to avoid methyl group loss, but the etch by-product removal capability is reduced also. Even with softer cleaning, the trench and via profile still will be affected due to ULK film...
Gate last approach has started to appear in the high performance applications since 45nm technology node. Such approach has to leverage soft wet and asher process for the polymer and byproduct removal after the 2nd DPGR for the 1st DPGR metal damage concern. However, it's well known that it's hard for soft wet process to remove all byproduct. Even worse, the rich polymer inside trench could result...
When CMOS technologies entered nanometer scales, FinFET has become one of the most promising devices because of its superior electrical characteristics. To accommodate the 3D topography, gate etch needs soft landing on the top of Fin while removing the extra poly-si around Fin. Its over etch is more aggressive than conventional planar gate to avoid poly-si residue. Fin loss should be well controlled...
Both shallow junction and HKMG have been integrated into the advanced logic process. This leads to the introduction of forming gas (4% H2 in N2/H2 mixture) to replace the traditional O2-based ashing process for the sake of material loss and metal oxidization in Lightly Doped Drain ash. In this work, we focused on the high volume H2 ashing not only from the point of view of physical performance but...
Since CMOS technology moved to sub-40nm node and beyond, the remarkable challenges have been noticed in dry etch, wet clean and the subsequent metal deposition process of contact loop. Contact etch has been proven as one of the most critical roles for yield enhancement. It not only needs to overcome the incoming challenges such as poor PR profile/CDU and CESL (Contact Etch Stop Layer) nitride pinch-off,...
A torsional wear and friction simulator with a ball on flat polymer was developed to analyze the tribological behavior of hip joints. Wear tests of polymethyl methacrylate (PMMA) against GCr15 (AISI 52100) steel and PMMA molecules (both with diameters of 40mm) were conducted. Based on the analysis of frictional kinetics behaviors, and observations of three-dimensional (3D) profiles and SEM morphologies,...
65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch...
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