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This article presents a simple, non-toxic, and low-cost tips arrays made of poly-dimethylsiloxane pyramidal material, which is expected to have a large-scale application in the future civil biomedical field. A layer of silica and silicon nitride are grown on the silicon wafer as a corrosion mask by thermal oxygen and low pressure chemical vapor deposition process, sequentially. After lithography process,...
This paper develops a bumpless wafer-on-wafer (WoW) memory integration approach in order to increase its throughput and reliability without sacrificing the electrical and mechanical performances compared to the bump-containing chip-on-chip (CoC) integration. The features are that through silicon vias are bottom–up filled after multilayer wafers bonding and connected to the predeposited redistribution...
Flip-chip bonding has become an efficient method to realize fine-pitch interconnection in high density interconnection applications. Thermal-compression bonding of Cu/Sn microbumps can induce extra thermal stress because of high bonding temperature, long bonding time and high bonding force. Temperature, time and force are expected to be decreased to improve the thermal-mechanical reliability of the...
In this paper, a TGV interposer based wafer level packaging for inertial MEMS devices is presented. For the TGV interposer, there is a redistribution layer of Al wiring on each side, which are electrically connected with Al metalized TGV. Being as a capping wafer, it's bonded to a MEMS accelerometer wafer based on bulk silicon process with a patterned benzocyclobutene(BCB) layer to achieve wafer level...
In this paper, a simplified process for TGV interposer is presented for RF applications. Sand blasting method and thinning/polishing process is utilized to form TGVs on Glass wafer. TGV interposer metallization of is realized with Al sputtering followed by wet chemical etching. Based on the process, TGV interposer is fabricated and the TGV sample measures about 361µm in the diameter at the front side,...
Bulk tungsten is very promising for packaging and micro-devices for its high strength, radiation resistance, high melting point and conductivity. In this paper, chemical mechanical polishing of bulk tungsten substrate was carried out. A 4 inch tungsten wafer was polished at the optimized condition with an average surface roughness of 4.63nm achieved. Bulk tungsten applications in packaging and micro-devices...
The modified sepiolite clay catalyst cleaned by nitric acid, impregnated copper nitrate, drying and then calcinations, combined with non-thermal plasma produced by dielectric barrier discharge reactor to remove NO. With XRD analyzed pattern of original and modified sepiolite, the Mg element and others were effectively removed from the original sepiolite by cleaning with nitric acid; the stable phase...
The analyses of machining allowance of the auto-panel die blank casting in rough processing was discussed in this paper. And a method was developed to get the roughly uniform allowance and the excessive allowance was transferred to the bottom plane of the cast blank, which can be cut rapidly by the general machine tool with the large feed & high removal rate process. An analyses example of metal...
This paper reports the characterization of bulk titanium deep etching using inductively coupled chlorine plasma using SU-8 as softmask. SU-8 has many advantages over the traditional employed hardmask, such as selective stripping, cost efficiency and the ability to accommodate ultra deep etching. The effects of process parameters (ICP source power, platen power and Cl2 flow rate) on etch rate, selectivity...
Nanostructured titania (NST) is attracting more and more attention due to its porousness and high surface to volume ratio. A novel process to fabricate integrated NST thin film at low temperature (80-90??C) is presented. NST features were formed by oxidizing Ti films in aqueous hydrogen peroxide. The optimal conditions of aqueous oxidation are: 85??C, aqueous 10% H2O2 solution, 20 min of water bath...
In this paper, wafer bonding using Parylene as the adhesive layer is investigated. The experiments are carried out under various conditions in two approaches: Parylene-to-Parylene and Parylene-to-Silicon. By heating at 230??C and applying a bonding force in vacuum environment, both Parylene-Parylene and Parylene-Silicon are successfully bonded. The bonding quality is characterized by the joint area...
We present a novel method to realize 3D adiabatically Spot-Size Converter (SSC) structures by standard silicon micromachining technics, for efficient coupling from single-mode fiber or free-space to silicon photonic chip. The SSC is comprised of I/O waveguides and a 3D tapered coupler on silicon-on-insulator (SOI) substrate. The dimensions are decreased linearly in both vertical and horizontal directions...
As MicroElectroMechanical Systems become more complicated, building them as integrated systems may not be possible and exploring new microassembly technologies becomes necessary. A novel flip-chip assembled microplatform combined with a microjig and alignment pairs is presented, both of which are fabricated with room-temperature, non-aggressive processes that can accommodate a board range of devices...
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