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Localized small delay defects, for example due to degraded transistor drive strength caused by a broken fin, are a growing concern in current FinFET and emerging gate all around (GAA) technologies. Such defects are currently targeted by timing-aware Transition Delay Fault (TDF) tests that aim to test the target nodes along the longest path. The resulting tests often require considerable test generation...
Negative bias temperature instability (NBTI) is a key reliability issue in deep sub-micron technology nodes. Identifying NBTI induced high variability timing-critical paths in stipulated design cycle time is a real challenge for System-on-Chip (SoC) designers. Firstly, we identify those device parameters that must be considered while performing statistical simulations to estimate maximum path delays...
System-on-Chip is a promising model for design of complex integrated circuits. In this model, designers may easily incorporate licensed and/or purchased Intellectual Property (IP) modules from other vendors to significantly reduce the design cycle time. However, the need to fulfill the legal obligations in the associated license or purchase contracts usually imposes considerable burden on the design...
Sensing devices can be deployed to form a network for monitoring a region of interest. This chapter investigates the detection of a target in the region being monitored by using collaborative target detection algorithms among the sensors. The objective is to develop a low cost sensor deployment strategy to meet a performance criteria. A path exposure metric is proposed to measure the goodness of deployment...
Iterative solvers are typically used to solve linear systems involving large coefficient matrices. In recent years, graphics processing units (GPUs) have become a popular platform for scientific computing applications, and are increasingly being used as the main computational units in supercomputers. However, GPUs are becoming more vulnerable to transient faults caused by events such as alpha particle...
In some complex deep sub-micron designs, the variations in interconnect delay has a significant impact on the production yield of the product. In this paper, we develop a theoretical explanation for the unexpectedly higher process related timing variability shown by long interconnects that are driven by high drive strength gates. This gets even worse due to conventional gate delay variability and...
It is very difficult, if not impossible, to design hazard free circuits in view of substantial delay uncertainties of gates and interconnects implemented in sub micron technologies. In this paper, we propose diagnosis methods for gate delay faults for such circuits. The fault simulation method employed by us uses eight values and calculates logic values as well as earliest transition times and latest...
Mobile devices are now very popular in many applications, and there is a trend to use them in statistic surveys. The main technical issue is privacy assurance. In this paper, we propose a certification-based approach for privacy assurance in multiple transactions of a survey conducted by a third-party application (TPA), which wants to find the maximal values of private data of some member groups in...
A typical real-time application is composed of periodic tasks with hard deadline constraints. It must also service a periodic tasks that are generated in response to external and internal events. In addition to application's timing constraints, it is important that the system never violates thermal constraint due to its increasingly adverse impact on the processing platform. In this work, we propose...
As Integrated Circuits (ICs) become more complex through smaller semiconductor feature sizes and higher performance requirements, the thorough testing of silicon devices is becoming a greater economic challenge. System-on-Chip (SoC) test schedules not only need to achieve the shortest possible test application time, they must also satisfy new design constraints which are increasing test scheduling...
With growing need to address the thermal issues in modern processing platforms various performance throttling schemes have been proposed in literature (DVFS, clock gating etcetera). In real-time systems such methods are often unacceptable as they can result into potentially catastrophic deadline misses. As a result real-time scheduling research has been focused in developing algorithms which meet...
This paper presents a diagnosis method for gate delay faults in the presence of clock delay faults. The method deduces candidate faults using a single gate delay fault dictionary and a single clock delay fault dictionary, which contain the information of latest transition time of signals as well as output logic values. To reduce the diagnostic ambiguity we remove those faults from the candidate fault...
Due to rapidly increasing power densities in Integrated Circuits (ICs) and the resulting increases in on-chip temperatures, thermal management has become an important issue in embedded system design. This paper focuses on thermal aware scheduling of periodic real-time tasks in embedded systems. The paper exploits a concept called Total Thermal Impact of a periodic task set to develop some theoretical...
Increasing design complexity coupled with new design and manufacturing techniques being used for modern integrate circuits is creating challenges for test environment. The goal of system-on chip (SoC) test scheduling has always been to reduce test application time. Added design constraints for SoC environment are making this scheduling more difficult. This difficulty is increased by manufacturing...
Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant...
Various techniques for modern high performance designs, such as clock gating and dynamic voltage frequency scaling (DVFS), have been adapted to address power issues. This is a consequence of technology scaling and it is important and desirable to address reliability needs as well as economic issues. From a testing point of view, introduction of power constraints during testing is needed for the desired...
In this paper we introduce a novel characterization of real-time tasks based on their temperature impact. This characterization is used to analyze the schedulability of periodic real-time tasks in thermally constrained systems. The proposed characterization is important because thermal constraints are becoming increasingly vital due to rapid and increasing rise in power densities of modern architectures...
In this paper we investigate a method of scheduling aperiodic tasks with a given periodic schedule, in a thermally constrained embedded real-time system. Considering thermal constraints is important for current and future processing systems because of the rapid rise in the power densities of processors, especially in multicore environments. Therefore, if thermal constraints are not considered, processor...
With technology scaling towards smaller geometries, the power density of modern integrated circuits (ICs) can potentially result into high temperatures during test, a problem further compounded by stacking dies in 3D stacked structures (3DSICs). Scheduling tests in a way to minimize the total test time becomes a key issue when temperature constraints are involved, since a more compact schedule leads...
This paper presents diagnosis methods for bridging faults between a clock line and a gate signal line. Scan-based simulation methods are applied while assuming that only scan-based flush tests are used. In view of the fact that initial states play an important role, we consider two possible scenarios: 1) all flip-flops are assumed to be reset table, and 2) flip-flops are not reset table. In order...
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