System-on-Chip is a promising model for design of complex integrated circuits. In this model, designers may easily incorporate licensed and/or purchased Intellectual Property (IP) modules from other vendors to significantly reduce the design cycle time. However, the need to fulfill the legal obligations in the associated license or purchase contracts usually imposes considerable burden on the design process. The burden is often in the form of design access constraints that have to be imposed on SoC design team and/or in the form of additional costs needed to acquire a less constraining contract. To alleviate these problems, this paper proposes a encryption approach that assures confidentiality of the gate-level circuit information for the module designer while allowing the SoC designers an ability to perform gate-level digital simulations with gate-level delays. Empirical evaluation on benchmark circuits shows that, in addition to not being able to identify the gate types, an attacker cannot decrypt the delays associated with most of the gates in the circuit.