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In this paper, a new and simple method named Weibull criterion is proposed to identify whether metastable states occur in single random telegraph noise (RTN), which has been verified by both simulation and experiment results. It is helpful for comprehensive understanding of trap properties and providing a direct evidence of oxide traps with multiple states.
In this paper, it is reported for the first time that, in nanoscale high-k/metal-gate MOSFETs, the hot carrier degradation (HCD) follows a two-stage law in some stress conditions. Both interface traps and oxide traps contribute to HCD causing its time-dependence varies with different stress modes. The results are helpful for the physical understanding of HCD in nanoscale devices.
In this paper, a new steep-slope device concept of resistive-gate field-effect transistor (RG-FET), which is operated by electrically induced abrupt resistance change of gate stacks, is discussed in detail and experimentally optimized. The fabricated RG-FET demonstrates both an ultra-steep subthreshold slope of below 5mV/dec over almost 2 decades of drain current and a high on-current competitive...
In this paper, the widely adopted “hole in the inversion layer” (HIL) model for predicting the amplitude of random telegraph noise (RTN) in nanoscale MOSFETs, is theoretically revisited with focusing on its scaling limit and validation range. It is found that this simple physical model fail to apply on ultra-scaled devices with L<20nm and/or W<10nm, due to the non-negligible impact from source/drain...
The frequency dependence of the single-trap induced degradation (STID) are investigated both experimentally and theoretically, which is the key for the understanding of AC NBTI characteristics and temporal variations. Instead of the conventional 2-state trap model (2SM), the 4-state trap model (4SM) are studied through Monte-Carlo simulation in detail, which give a reasonable interpretation of the...
A new variation-aware energy-delay optimization method is proposed for device-circuit co-design in nanoscale CMOS digital circuits design. Yield is added into traditional energy-delay (ED) optimization method as a figure of merit to take account of ED variation caused by major process variation sources in nanoscale technology. Threshold voltage and supply voltage can be co-optimized to meet any customized...
For decades, advances in integrated circuits (IC) have been driven by continuous scaling down of planar IC technologies. As IC scaling rapidly approaches to technical brick wall, 3D IC heterogeneous integration emerges as a viable solution for future integrated electronics. Future complex system-on-a-chip (SoC) requires high-performance active devices, and novel passive and supporting devices. This...
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
We investigated source potential impacts on drain disturb of NOR Flash cells and proposed a novel source-biased measurement which can separate channel leakage current disturb and band-to-band disturb. By this method we explored the origins of drain disturb of Nanoscale Flash Memory. Our results indicate that, under channel ionized secondary electron (CHISEL) injection operation, drain disturb originates...
The ballistic efficiency and self-heating effects in gate-all-around silicon nanowire transistors (SNWTs) are experimentally investigated in this paper. A modified experimental extraction method for SNWTs is proposed, which takes into account the impact of source contact resistance. The highest ballistic efficiency is observed in sub-40 nm SNWTs at room temperature, demonstrating their intrinsic potential...
Impacts of electron trapping/detrapping on the negative bias temperature instability (NBTI) characteristics in silicon nanowire transistors (SNWTs) with metal gates are experimentally studied in this paper. It is demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanowire structure due to multiple surface crystal orientations of the cylinder...
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