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In this paper, it is reported for the first time that, in nanoscale high-k/metal-gate MOSFETs, the hot carrier degradation (HCD) follows a two-stage law in some stress conditions. Both interface traps and oxide traps contribute to HCD causing its time-dependence varies with different stress modes. The results are helpful for the physical understanding of HCD in nanoscale devices.
The frequency dependence of the single-trap induced degradation (STID) are investigated both experimentally and theoretically, which is the key for the understanding of AC NBTI characteristics and temporal variations. Instead of the conventional 2-state trap model (2SM), the 4-state trap model (4SM) are studied through Monte-Carlo simulation in detail, which give a reasonable interpretation of the...
In this paper, the effects of nanowire line-edge roughness (LER) in gate-all-around silicon nanowire MOSFETs (SNWTs) are comprehensively investigated through 3-D statistical simulation. The LER impacts on both the device performance variation and mean value degradation are discussed in detail. Due to the unique nature of a nanowire structure, the LER in SNWTs contains two degrees of freedom, which...
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