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This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.
We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.
Continuous scaling down NAND FLASH toward below 2Xnm node generation will result in serious Floating Gate (FG) poly depletion due to dopant loss and significantly degrade the cell reliability performance. FG implantation (IMP) before inter-poly-dielectric (IPD) deposition was proposed in this study, but it suffered FG damage and resulted in control gate (CG) void issue. We have successfully minimized...
A novel three-dimensional (3D) NAND structure containing both vertical gate (VG) framework and gate-all-around (GAA) cell structure is innovated and demonstrated. It is fabricated on alternating layers of silicon dioxide (OX) and polysilicon (PL) by using 43nm technology. To our knowledge, one of the major advantages of the novel structure is the smaller cell unit footprint than vertical channel (VC)...
Pattern dependent charging effect is explored in this study. Due to increased film thickness in 3D NAND structure, a derivative problem-the plasma-induced charging damage is enhanced during high aspect ratio (HAR) etching. In this paper, several effective methods are demonstrated to alleviate the impact of profile distortion due to charging effect while etching high aspect ratio (>14) trenches.
NF3/NH3 remote plasmas are used in oxide etch back process prior to the salicide process of word lines (WL) owing to high etch selectivity of silicon oxide over polysilicon. The etch saturation behavior which performs etch stop with a certain period of process time is one of the interesting characteristics during oxide etch process by employing NF3/NH3 remote plasmas. In this study, it is found that...
Thickness variations of ILD CMP induced yield loss at wafer edge is simulated by 3D Sentaurus Interconnect, in order to achieve more authentic condition, we adopt the image contour extraction technique to stream the genuine contact contour gds together with STI, POLY, ML database. The results demonstrates that when the thickness is over 7k at wafer edge, there is no electric current found, and it...
Down-flow plasma etching is mentioned instead of high-density capacitively coupled plasma (CCP) etching to prevent the control gate (CG) against physical damage during the intra-level dielectric (ILD) etch back, which is the process prior to form cobalt silicide word lines. However, owning to lack of ion bombardment, it is hard to achieve good etch uniformity. This paper presents the design of experiments...
Severe and unexpected yield loss (∼26% in avg.) is found in the early development stage of the advanced flash memory. The major failure mode, array bridging contact, is revealed as the root cause and mainly induced by undercutting photo-resist (PR) profile. In this work, a novel scheme, anti-etch bottom anti-reflective coating (anti-etch BARC), is used instead of the conventional dual ARC (BARC/dielectric...
Airborne molecular contamination (AMC) becomes more serious in Fab as the device shrinks and wafer size increases, an economic way for preventing these contaminations is to use N2 purge charging process. The practical FOUP N2 purge engineering is addressed here, which includes the maintenance and management of FOUPs, N2 purge charging flow rate, the design of nozzle, selection of nuzzle material,...
A novel formation method of long-period fiber gratings (LPFGs) based on periodic microchannels, which are fabricated by femtosecond laser micromachining and selective chemical etching in conventional single-mode fibers, is proposed and experimentally demonstrated. This kind of grating may be as short as only 3 mm and exhibits low-temperature sensitivity of 9.95 from 30 ...
Advanced bright field (BF) inspector have many functions to increase the defect signal, and suppress the background noise. However, it will take much time to fine tune an optimized BF inspection recipe. The aim of this paper is to propose a faster way to select the optimized optics.
The topic of this paper is to identify tungsten plug corrosion issue at the interface of barrier metal and W bulk in W-CMP process. Two types of nucleation layers in W-CVD deposition process - SiH4 and B2H6 based were studied. The B2H6 based nucleation W will induce W corrosion. However, SiH4 based nucleation W does not have the issue. The static etch rate, electrochemical properties and removal rate...
The authors investigated the correlation between variation of post-etch critical dimension (ECD) and etcher chamber condition during floating gate etching process. This paper presents the significantly effective method of utilizing the SF6/O2-based very long plasma-chamber cleaning or the novel Transformer coupled plasma (TCP) window temperature design not only achieves a stable gate CD (CD variation...
This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional...
This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger...
This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon...
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