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With shrinking design rules, the latest bare wafer surface inspection tools are driving sensitivity to less than 20nm. Fabs have also improved particle control—sometimes the biggest particle size is only ∼30–50nm. KLA-Tencor's SEM Review tool uses an improved alignment system and high sensitivity optical microscope (OM) to identify ∼30nm particle. The review system also provides a real-time automatic...
The application of correcting small temperature non-uniformity on Silicon wafers using local irradiation with spatially scanning laser beams was analyzed. The objective of the study was to understand the specifications of such a laser beam to elevate the temperature of a wafer locally by 1 to 5°C. A detailed analytical model has been developed for predicting power level, exposure time, scanning speed,...
Time dependent second harmonic optical signals were measured across silicon-on-insulator (SOI) wafer coupons contaminated by Cu-63 ion implanted into the buried oxide (BOX) and near the SOI/BOX and BOX/Bulk interfaces. Average signals after 1 second of exposure for all spatial points were compared between wafers and used to differentiate contamination levels post ion-implantation.
This paper provides an overview and details concerning a new and fundamentally based solution concept to support “real” real-time Fab analysis, fast new-product ramp and inherent knowledge discovery. Basic use cases and business drivers will be highlighted, and some insight will be given into a new and mathematically grounded system and methodology. Influences of database technologies will be discussed,...
Implantation equipment is expected to possess the highest possible productivity due to the short process time in a semiconductor manufacturing factory. The setup time of implantation plays a more important role in improving tool productivity as compared with other processes. Dedicated tools for individual recipe groups avoid setup occurrence but lead to low tool utilization and high equipment cost...
Like the 300mm standards, the 450mm physical interface standards define the multitude of parameters that are essential to factory automation and interoperability. In addition, 450mm standards drive factory efficiency much farther than the 300mm standards did. This paper will review the standards architecture and critical parameters defined by the standards with a focus on the efficiency improvements...
Advanced process control (APC) is widely used in semiconductor manufacturing to adjust process parameters, ensuring a high product quality, while WIP flow optimization systems for scheduling & dispatching make decisions by assigning lots to tools for processing. APC imposes additional constraints to the operational decisions. It is critical to understand the relationship between these two aspects...
In this paper, production of lots under time constraints in a semiconductor wafer fabrication is investigated. A time constraint covers a sequence of process steps and has a maximum time that lots must spend in these steps. Lots which violate a recommended time constraint have to be scrapped or reprocessed. Accordingly, controlling the entrance of lots in a time constraint is critical in semiconductor...
Stand-alone Electrically Erasable Programmable ROM (EEPROM) are widely used in industrial, automotive and portable consumer applications. Requirements for high density EEPROM have been steadily increasing in recent years. As deep submicron nodes are used to achieve highly dense bit-cells, the propensity for process-induced defects associated with compact isolation rules and architecture also increase...
In this paper, the observation of active area line collapse in 20 nm planar NAND Flash technology is reported. The mechanism of active area pattern collapse is described using the theory of capillary forces. The proposed model for pattern collapse is validated by data obtained by real time defect analysis and end of line electrical data. Next, with the help of an empirical model, key structural metrics...
This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail - sensitivity to time, design...
Design Hotspots are features on a silicon chip, which are susceptible to pattern failures. While multiple methods like DRC, ORC and CFM inspection are used to identify these Hotspots, in-line monitoring of these design Hotspots has remained a challenge. Existing methods of Hotspot inspection, which include API and EBI are not suited for large scale inspection due to system limitations and throughput...
In this paper we evaluate the Reticle Defect Review feature on KLA-Tencor's e-beam review tool, eDR™-7110, and study defect printability of reticle defects on wafer. The RDR feature is able to read KLA-Tencor's reticle inspection results directly without any intermediate format, thus allowing what-you-see-is-what-you-get setup on the wafer review tool. Compared with a conventional reticle to wafer...
Reducing focus errors during optical lithography patterning is crucial for minimizing defects and for achieving the desired critical dimension uniformity (CDU). Factors that contribute to lithography defocus originate from both within and outside the exposure tools. Wafer geometry and topography have been shown to be a major contributor to the focus budget, but decoupling wafer issues from scanner...
The growing complexity of photolithography processes necessitates stringent defect monitoring to meet the increasingly rigorous yield requirements. Mitigation of defectivity at the track level involves both product wafer scans, as well as blanket wafer inspections for process monitoring and tool qualification. Some of the common defect types that are characteristic of the track process are comets,...
Rapid Defect source tool identification in semiconductor manufacturing is crucial to improve the product quality and to reduce the production cost. When defect is detected, tool commonality among lots is a proven technique to identify the defect source. The critical element of successful commonality analysis is the multiple entry lots within the same process flow. Hence, since deployment of dynamic...
Climate change, as a consequence of increased greenhouse gas emissions, is a growing concern. Reducing energy usage in semiconductor manufacturing is an effective way to be responsive to this global issue and reduce costs.
Unexpected yield loss in high-volume DRAM manufacturing occurs very often as an excursion in critical levels such as high aspect ratio container (HARC) etch in capacitor formation in the device. The main failure mode is polymer formation and plasma density change during the chamber preventive maintenance. In this paper we study the effect of polymer formation on HARC profile at various electrostatic...
In this paper, we studied defect discovery and defect review using back-scattered electron (BSE) images. We found that some defects can only be effectively imaged with BSE mode such as hafnium oxide remain at metal gate chemical mechanical polishing (CMP) in the gate last high-k metal gate (HKMG) process. It can also enhance contrast for materials in the bottom of high aspect ratio (HAR) trenches...
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