Takahiro Hanyu

article

Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, more

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2017 > 25 > 10 > 2724 - 2735

This paper introduces area/energy-efficient gammatone filters based on stochastic computation. The gammatone filter well expresses the performance of human auditory peripheral mechanism and has a potential of improving advanced speech communications systems, especially hearing assisting devices and noise robust speech-recognition systems. Using stochastic computation, a power-and-area hungry multiplier...

article

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Arash Ardakani, Francois Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, more

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2017 > 25 > 10 > 2688 - 2699

The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing (SC) has shown promising results for low-power...

chapter

Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability

Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference > 43 - 46

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference (ESSCIRC)

This paper introduces an accuracy/energy-flexible configurable 2D Gabor filter based on stochastic computation, where bit streams representing information are used. The Gabor filters show a powerful feature extraction capability, but the calculation based on binary computation is complicated. As opposed to traditional memory-based methods that use fixed Gabor coefficients calculated by software in...

chapter

MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures

Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda

2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) > 118 - 125

2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

This paper introduces CMOS/magnetic tunnel junction (MTJ)-based asynchronous single-track circuits for re-initialization free computing against power failures. In energy-harvesting applications, data processed might be lost due to frequent power failures, which usually requires the initialization phase after the power supply is recovered. To prevent the re-initialization for energy-efficient computing,...

chapter

Evaluation of Stochastic Cascaded IIR Filters

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, more

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL) > 224 - 229

2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)

Stochastic cascaded IIR filters are used for area-efficient complicated filters in hardware, such as gammatone and gammachirp filters, but the effectiveness of the cascaded form has not been studied in stochastic computation. To evaluate the performance of the stochastic cascaded IIR filters, stochastic direct-form IIR filters are also designed as a baseline filter. The performance of both stochastic...

article

Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

IEEE Transactions on Emerging Topics in Computing > 2017 > 5 > 2 > 151 - 163

This paper introduces a sudden power-outage resilient in-processor checkpointing for energy-harvesting nonvolatile processors. In energy harvesting applications, a power supply generated from a renewable power source is unstable that may induce frequent sudden power outages, causing the inconsistency among distributed nonvolatile flip-flops (NVFFs) and hence failure rollbacks in conventional nonvolatile...

chapter

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 > 548 - 553

2017 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Magnetic-Tunnel Junction (MTJ)-based non-volatile logic circuits have some possibility to solve the power-dissipation problem seriously focusing on the present CMOS-only-based VLSI processors. Three terminal MTJ devices are the promising candidate as nonvolatile storage device to realize such a nonvolatile logic circuit. However, its writing energy is still serious in comparison with conventional...

article

A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception

Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, more

Journal of Signal Processing Systems > 2018 > 90 > 5 > 709-725

Implementing neuromorphic algorithms is increasingly interesting as the error resilience and low-area, low-energy nature of biological systems becomes the potential solution for problems in robotics and artificial intelligence. While conventional digital methods are inefficient in implementing massively parallel systems, analog solutions are hard to design and program. Stochastic Computing (SC) is...

article

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, more

Proceedings of the IEEE > 2016 > 104 > 10 > 1844 - 1863

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture...

chapter

VLSI implementation of deep neural networks using integral stochastic computing

Arash Ardakani, Francois Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, more

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC) > 216 - 220

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)

The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention since many applications require high-speed operations. However, numerous processing elements and complex interconnections are usually required, leading to a large area occupation and a high power consumption. Stochastic computing has shown promising results for area-efficient hardware implementations,...

article

Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips

Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu

IEEE Transactions on Nanotechnology > 2016 > 15 > 5 > 705 - 714

This paper introduces an analog-to-stochastic converter using a magnetic tunnel junction (MTJ) device for vision chips based on stochastic computation. Stochastic computation has been recently exploited for area-efficient hardware implementation, such as low-density parity-check decoders and image processors. However, power-and-area hungry two-step (analog-to-digital and digital-to-stochastic) converters...

chapter

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

Daisuke Suzuki, Takahiro Hanyu

2016 26th International Conference on Field Programmable Logic and Applications (FPL) > 1 - 4

2016 26th International Conference on Field Programmable Logic and Applications (FPL)

A nonvolatile field-programmable gate array (NVFPGA), where both magnetic tunnel junction (MTJ) devices and greedy power-saving techniques are utilized, is proposed. Because the circuit components are shared among several MTJ devices by the use of logic-in-memory (LIM) structure, the number of leakage current paths is reduced, which results in leakage power reduction during power-on. Moreover, the...

chapter

A study of a top-down error correction technique using Recurrent-Neural-Network-based learning

Masanori Natsui, Naoto Sugaya, Takahiro Hanyu

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS) > 1 - 4

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)

A new error correction scheme based on a brain-inspired learning algorithm, called Recurrent Neural Network (RNN), is proposed for resilient and efficient intra-chip data transmission. RNN has a feature to find partially-clustered time-series data stream and predict the next input data from previous input data stream. By utilizing this feature, a novel top-down error correction approach which considers...

chapter

Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations

Naoya Onizawa, Takahiro Hanyu

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS) > 1 - 4

2016 14th IEEE International New Circuits and Systems Conference (NEWCAS)

This paper introduces redundant spin-transfer-torque (STT) magnetic tunnel junction (MTJ) based nonvolatile flip-flops (NVFFs) for low write-error rate (WER) operations. STT-MTJ NVFFs are key components for ultra-low power VLSI systems thanks to zero standby current, but suffers from write errors due to probabilistic switching, causing a failure backup/restore operation. To reduce the WER, redundant...

article

An Overview of Nonvolatile Emerging Memories— Spintronics for Working Memories

Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, more

IEEE Journal on Emerging and Selected Topics in Circuits and Systems > 2016 > 6 > 2 > 109 - 119

This paper reviews emerging nonvolatile random access memories (RAM) in recent years. It first benchmarks ferroelectric RAM (FeRAM), phase change RAM (PCRAM), resistive RAM (ReRAM), and spin-torque-transfer magnetic RAM (STT-MRAM), discussing each RAM's features and its applications. Then current status of spintronics developments including not only STT-MRAM but also nonvolatile logic LSI is described,...

chapter

Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation

Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, more

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) > 223 - 228

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)

Recently, some attempts have been made to apply stochastic computation to realization of Finite Impulse Response (FIR) digital filters. Such new FIR filter realizations lead to significant reduction of hardware complexity over the conventional filter realizations based on binary computation. However, the stochastic FIR filters suffer from lower computational accuracy than the FIR filters based on...

chapter

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme

Daisuke Suzuki, Takahiro Hanyu

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) > 5 - 10

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)

An energy-efficient and highly-reliable nonvolatile FPGA using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular logic cluster is completed,...

chapter

Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission

Naoto Sugaya, Masanori Natsui, Takahiro Hanyu

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL) > 72 - 77

2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)

An error correction scheme utilizing a brain-inspired learning algorithm, called Recurrent Neural Network (RNN), is proposed for resilient and efficient intra-chip data transmission. RNN has a feature to find partially-clustered time-series data stream from an input data stream and predict the next input data from previous input data stream, which can be utilized for realizing an error correction...

article

Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks

Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross

IEEE Journal on Emerging and Selected Topics in Circuits and Systems > 2016 > 6 > 1 > 13 - 24

This paper presents algorithms and hardware implementations of associative memories based on multiple-valued sparse clustered networks (MV-SCNs). SCNs are recently-introduced binary-weighted associative memories that significantly improve the storage and retrieval capabilities over the prior state-of-the art. However, deleting or updating the messages stored in binary-weighted connections result in...

chapter

Gammatone filter based on stochastic computation

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, more

2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) > 1036 - 1040

ICASSP 2016 - 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

This paper introduces a design of a gammatone filter based on stochastic computation for area-efficient hardware. The gammatone filter well expresses the performance of human auditory peripheral mechanism and has a potential of improving advanced speech communications systems, especially hearing assisting devices and noise robust speech recognition systems. Using stochastic computation, a power-and-area...

INFONA - science communication portal

Search results for: Takahiro Hanyu

Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability

MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures

Evaluation of Stochastic Cascaded IIR Filters

Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor

A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

VLSI implementation of deep neural networks using integral stochastic computing

Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

A study of a top-down error correction technique using Recurrent-Neural-Network-based learning

Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations

An Overview of Nonvolatile Emerging Memories— Spintronics for Working Memories

Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme

Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission

Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks

Gammatone filter based on stochastic computation

Filter options

Publication date

Publication type

Keywords

Data set

Journal

INFONA - science communication portal

Search results for: Takahiro Hanyu

Add recipient

Sending message cancelled

Are you sure you want to cancel sending this message?

Send message

Filter options

Publication date

Date range setting

Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.

Publication type

Keywords

Data set

Journal

Reporting an error / abuse

Sending the report failed

Accessibility options