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This paper proposes a method for analyzing the power supply impedance at an on-chip power supply node in the device under test. The proposed method is based on an on-chip power measurement of a power supply voltage fluctuation with sweeping the frequency of the on-chip current load which sinks a square wave current, not sinusoidal. The method can extract the frequency characteristics of not only the...
This paper presents a PWPLL (Pulse-Width Controlled PLL) using a variable-length ring oscillator for autonomously tracking PVT (Process, Voltage and Temperature) variations. We fix the ring oscillator control code and the numbers of the reference CLKs and the feedback CLKs are compared, and then the additional Tracking Circuits switch the number of stages for a PWPLL to be locked. The PWPLL using...
This paper proposes an on-chip measurement method of PLL transfer function. In our proposed scheme, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the amplitude domain and the phase domain. Since the DTC and...
This paper proposes an active resonant power supply noise cancelling with fast voltage drop sensor using the combination of delay-locked loop (DLL) and vernier time-to-digital converter (TDC). Also, we propose the capacitor selector circuit realizing the active insertion of capacitors in less silicon area. These components enable one clock noise detection with fine resolution. Simulation results show...
Stochastic TDCs excel in high resolution at narrow dynamic ranges by employing comparators which have their decision influenced by PVT variations. As the functionality relies on these variations, a transfer function akin to the Gaussian distribution ensues, which is non-linear. We propose a theoretical derivation of the non-linearity analysis and use it to find the stochastic TDC's effective resolution...
An asynchronous projection and summation circuit is proposed for single photon avalanche diode (SPAD) sensors. Thanks to the efficient interconnection by the asynchronous technique, the circuit can be easily implemented inside 2D SPAD arrays. As a result, the precise summation of the 1b data in one row can be parallel processed for all rows within the same cycle. A test-of-concept chip was fabricated...
This paper demonstrates an on-die STO thin film decoupling capacitor used for resonant power supply noise reduction. The on-die STO capacitor consists of STO whose dielectric constant is about 20 and is sandwitched by Cu films in an organic interposer on which we can also draw connection wires by Cu deposition. The capacitor was attached directly on our test chip using ball banding technique through...
In this paper, we demonstrate our STO thin film decoupling capacitor embedded in organic interposer is effective for reduction of resonant power supply noise of LSI. By comparison of Shmoo plots with on-chip MOS capacitor, significant contributions of STO capacitor to higher operable frequency and lower power supply voltage are shown.
This paper demonstrates our dynamic power integrity control for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the device under test (DUT). It injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform...
We gave a weekly lecture 10 times in raw using Ustream. The text, slides were uploaded in advance on our web site, and the students asked questions through Twitter. We announced the lecture date and time by our mailing list, then more than 500 students registered and more than 150 students took the lecture in real time. The live streams were recorded and uploaded on Ustream site so that anyone can...
It is believed that the time-domain resolution of a digital signal edge transition is superior to the voltage resolution of an analog signal in advanced CMOS processes[1], [2]. The reasoning behind this is that operating voltage has been reducing, making the signal more vulnerable to noise power due to scaling. On the other hand, in time domain, scaling has resulted to increase in frequency and therefore...
This paper proposes a pulse width controlled Type-II PLL without using a charge pump nor a RC low pass filter. The loop filter is realized in a pulse width in time-domain instead of an analog voltage in voltage domain. The PLL has a pulse width P-I controlled oscillator whose oscillation frequency is controlled by two pulse widths, one of which is the PFD output pulse width (P), and the other is the...
This paper presents a Pulse Width controlled PLL which is designed by our customized automated flow. The Pulse Width controlled PLL (PWPLL) structure is a novel time-domain-based analog architecture which claims its small area, power and jitter. It is also compatible with standard-cell based design using a commercial P&R tool. Our design flow automatically synthesizes a circuit netlist, generates...
This paper demonstrates pulse width controlled PLL and DLL using a soft thermometer code. The oscillation frequency control in the PLL and the delay control in the DLL are conducted by a mostly digital with one bit analog code. Both of our PLL/DLL do not use an area-consuming capacitor, resulting in small silicon area implementation. A 65nm CMOS process uses only 120μm×30μm area for the PLL+DLL. They...
This paper presents a time-domain analog signal hold-and-replication circuit which holds an input time interval of two signal transitions and replicates it any number of times. The proposed Time Difference Hold-and-Replication (TDHR) circuit utilizes a dual pulse ring oscillator to hold the input time interval without any time deterioration due to mismatches. The proposed TDHR circuit is implemented...
This paper, as a case study and tutorial, discusses testing methods for general PLL features and their operating margin. These methods can be applied all for analog-, digital- and PW-PLLs. There are various kinds of on-chip measurement macros which can be applied for the PLL testing, and for the direction toward digitally assisted analog circuit testing, it is shown that a digitally controlled variable...
This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT). The proposed method controls the power supply voltage on an automatic test equipment (ATE) system in a feed-forward manner by supplying a compensation current into the power supply line based on the power supply voltage waveform difference between the...
This paper presents a digitally controlled arbitrary waveform generator whose output voltage range is 0 to 7.5V under a 1.2V supply voltage. The high output voltage generation is realized using only 65nm standard MOS transistors. It consists of a voltage increasing block and a voltage decreasing block to realize stable high voltage output. Experimental results show that our waveform generator can...
Moore's law keeps shrinking the transistor size, and timing degradation of the small transistors are becoming critical. Negative Bias Temperature Instability (NBTI) is one of the dominant cause degradation and increasing the path delay, resulting in timing errors. This paper introduces altered Fine-Grain Redundant (FGR) logic and Stress-balance Flip-Flops (SBFFs). FGR logic uses one of the two identical...
Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 65nm CMOS process. The proposed method achieves 46.9% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. The proposed method also realizes without discharging time before noise cancelling, and shows a 8.4× boost of...
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