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The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni3Si2 at the FUSI/dielectric interface is significantly widened for spike anneals (30degC < PW <...
The authors demonstrate a novel CMP-less FUSI integration scheme which uses a spin-on sacrificial material for planarization showing 45nm gate length Ni-rich FUSI pMOS and NiSi FUSI nMOS transistors on HfSiON. This new scheme does not require CMP but remains compatible with phase-controlled dual-WF CMOS with independent silicidation of the S/D and the gate. This approach uses very selective dry etch...
A study of the implementation of Ni fully silicided (FUSI) gates to scaled devices is presented, addressing the issue of phase control at short gate lengths. A linewidth effect for Ni FUSI gates is found for non-optimized processes targeting NiSi, with formation of NiSi at long gate lengths and Ni-rich silicides at short gate lengths. This is attributed to Ni diffusion from areas surrounding the gates,...
We demonstrate for the first time CMOS integration of dual WF (work function) metal gates on HfSiON using Ni-phase controlled FUSI. The novel integration scheme that we demonstrate uses our optimized 2-step Ni FUSI process (1) for simultaneous full silicidation of nMOS and pMOS, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled...
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