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The notion of Total Interference Degree (TID) is traditionally used to estimate the intensity of prevalent interference in a Multi-Radio Multi-Channel Wireless Mesh Network (MRMC WMN). Numerous Channel Assignment (CA) approaches, link-scheduling algorithms and routing schemes have been proposed for WMNs which rely entirely on the concept of TID estimates. They focus on minimizing TID to create a minimal...
Modern embedded systems are typically implemented using both programmable processors and application specific hardware in order to meet real time design goals, besides other metrics, such as, performance, area and cost. The availability of programmable processors and application specific hardware enables an application architect to partition the execution of the given application code (specified in...
Interdependence of the clocking architecture across IPs and overall peak power consumption is a major bottleneck that prevents concurrent yet independent testing of an IP at a higher clock frequency. We use a dynamic clocking architecture that eliminates these dependencies and reduces peak shift power by using clock phase staggering at a granular level during system-on-chip (SoC) testing. A SoC design...
Non-standardized scan interface within and across system-on-chips (SoCs) limits test-data reuse for intellectual properties (IPs). To overcome this limitation, we present a flexible and dynamic scan interface architecture that enables reuse of test-data for a given IP across SoCs with different scan pin configurations. The dynamic nature of this architecture also enables variable shift frequencies...
Embedded system design involves meeting strict design goals such as performance, area and power consumption. In-order to meet these design goals embedded systems are implemented in programmable processors and application-specific hardware. Hardware/Software partitioning is thus, a critical step in the realization of embedded systems. The initial software description of the application is profiled...
In recent years, 3rd Generation Partnership Project (3GPP) is taking on a pivotal role in standardizing the 4G network. Long Term Evolution (LTE) is a standard by the 3rd Generation Partnership Project (3GPP) and its main goal is to transform into 4G from mobile cellular wireless technology. Optimization of radio access techniques along with the improvement in the LTE systems lead 3GPP in developing...
A wide bandwidth VCO-based continuous-time ΔΣ modulator that uses combined phase and frequency feedback to mitigate VCO non-linearity and ease DEM timing requirement is presented. Fabricated in 65nm CMOS process, the prototype modulator operates at 1.2GS/s and achieves 71.5dB SNDR in 50MHz bandwidth while consuming 54mW of power, which translates to an FoM of 176fJ/conv-step.
A current sensing VCO based ADC architecture is realized using a passive integrator, VCO-based quantizer, and mostly digital circuits. A digital IIR filter is used instead of an analog loop filter to tackle VCO non-linearity in a power efficient and scaling friendly manner. The prototype circuit designed for an ambient light sensor application achieves 900pA accuracy over an input current range of...
In this brief, a design technique for high-speed pipelined analog-to-digital converters (ADCs) that enables processing rail-to-rail input swing without the use of dual set of reference voltages is proposed. The scheme not only operates on a single set of power supplies but also helps in power reduction in the ADC using a new multistage signal mapping technique aided by asynchronous sub-ADC quantization...
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