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In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation...
A novel impedance fault simulations methodology is presented in this paper. This methodology is based on an equation that calculates two-point impedance using the eigenvalues and eigenvectors of the circuit's nodal admittance matrix. This approach is applicable to active and passive circuits in both DC and AC domains. Possible applications of the proposed methods in the design of integrated circuits...
A novel resistance calculation method based on eigen calculus of the circuit's nodal admittance matrix is described and evaluated in this paper. More specifically, the calculation time efficiency of the method is examined and comparison to the traditional LU factorization based method is made. This evaluation is based on real and complex matrices that are both symmetrical and non-symmetrical as well...
This paper presents a novel wireless communication approach to modern households. A multi-standard wireless system concept for controlling and monitoring smart buildings is described. The goal of this paper is to point out the main issues regarding commonly used various home electronic systems, which leads to system complexity. Moreover, in the paper are presented solutions for the unification and...
The paper deals with the dynamic supply current testing (IDDT) of SRAM cells and arrays. An IDDT current sensor and sensing method are presented and explained. The effects of leakage current and static current consumption on the monitoring technique and efficiency are also discussed. The efficiency of the proposed test in unveiling weak open defects is demonstrated through simulations carried out...
Research presented in this paper is aimed at the comparison of the Oscillation-based Built-In Self Test (OBIST) efficiency in covering catastrophic and parametric faults in active analog integrated filters designed in two different technologies. Sallen-Key topologies of low-pass and high-pass filters were used as Circuit Under Test (CUT), designed in 0.35µm and 90nm CMOS technologies. The presented...
This paper presents a numerical approach to DC fault analysis of analog circuits that improves the total computational time and reduces the total complexity of such analysis. The reduction is achieved by utilization of calculus that can substitute conventional simulations and thus, significantly reducing computational time. A detailed description of the approach including its mathematical background...
This paper deals with a new readout interface of MEMS Capacitive Microphone (MCM) by presenting its general design as an application-specific integrated circuit (ASIC). The proposed frontend has been developed as an integrated part of the MCM microphone ASIC in order to be used in a noise dosimeter applicable in very harsh environment, e.g. minery. Therefore, the main attention has been paid to the...
In this paper, the design of a phase locked loop (PLL) with an additional lock detector with multiple output is presented. The proposed PLL is optimized for 2.5 V supply voltage and 20 MHz input reference signal. The PLL circuit also has 3 outputs of 170 MHz, 10.625 MHz and 10 MHz frequency. A lock detector is included in the PLL design, which indicates the lock state by generating logic 1 at its...
A new on-chip oscillation test strategy for analog and mixed-signal circuits is presented. In the proposed method, on-chip Schmitt trigger is used as the on-chip frequency reference to compensate the influence of process parameter variations. Furthermore, this solution also brings the possibility to implement Oscillation-based Built-In Self-Test (OBIST) for analog and mixed-signal integrated circuits...
This paper deals with the comparison of the fault coverage of catastrophic faults in active analog integrated filter obtained by the measurement of filter parameters and by the Oscillation-based Built-In Self Test (OBIST) approach. In our experiment, firstly, the cut-off frequency, ripple in the pass band, DC gain in pass band and group delay of the filters have been monitored in the operating mode...
Dynamic supply current test method (IDDT test) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the IDDT waveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of IDDT test in unveiling open defects was evaluated and the achieved...
This paper deals with the investigation of the fault detection in separated parts of a mixed-signal integrated circuit example by implementing parametric test methods. The experimental Circuit Under Test (CUT) consisting of an 8-bit binary-weighted R-2R ladder D/A converter and additional on-chip test hardware was designed in a standard 0.35µm CMOS technology. For detection of catastrophic and parametric...
In this paper, the dynamic supply current test (IDDT) for logic circuits is presented, where the targeted defects are weak opens in regular structures (SRAM arrays). Considerations about the current based tests are made, and a method of IDDT sensor realization is presented. The method is based on conversion of the current waveform to a voltage waveform. Also the most effective parameters of both the...
This paper deals with the design of a rail-to-rail operational amplifier (OPAMP) for a digital-to-analog converter. To achieve a low input offset of the OPAMP, a digital offset cancelation method has been proposed and used. The offset voltage in the range from −1.4 mV to 1 mV can be achieved. The OPAMP and additional hardware were designed in 90nm CMOS technology.
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