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Evaluating the resilience of a given circuit against adverse effects, such as radiation-induced single event upsets, is a complex and frequently time-demanding task. For Field Programmable Gate Arrays (FPGAs), this task has the additional complexity of accounting for faults affecting the configuration memory. For this reason, several works propose techniques to inject and evaluate faults affecting...
The use of embedded fault-tolerant mechanisms in Network-on-Chips (NoCs) has become essential to ensure connectivity in the presence of massive defects, and consequently improving the yield. According to the number of defects and their location in NoC, the fault tolerant techniques can be very expensive in terms of area, performance and energy overhead. The use of testing and diagnosis can help to...
The use of embedded fault-tolerant mechanisms in Network-on-Chips (NoCs) has become essential to ensure connectivity in the presence of massive defects, and consequently improving the yield. According to the number of defects and their location in NoC, the fault tolerant techniques can be very expensive in terms of area, performance and energy overhead. The use of testing and diagnosis can help to...
A novel fault-tolerant microprocessor capable of detecting and correcting radiation-induced soft errors is proposed and evaluated. The Resilient Adaptive Algebraic Architecture performs time redundancy in parallel with matrix multiplication computation, guaranteeing on-the-fly detection and correction of errors disrupting data and logic with minimum overhead. We evaluate the RA3 microprocessor in...
A novel fault-tolerant microprocessor capable of detecting and correcting radiation-induced soft errors is proposed and evaluated. The Fault-Tolerant Algebraic Architecture (FTAA) performs time redundancy intrinsically with computation, guaranteeing on-the-fly detection and correction of errors disrupting data and logic with minimum overhead. We evaluate the FTAA microprocessor in terms of performance,...
A novel software-implemented hardware fault tolerance method based on encoding both the control and the data-flow segments of programs with matrices is proposed and evaluated. Results show an average speed-up of 3 times compared to standard duplication and comparison, with coverage higher than 95% for the case studies considered, which outperforms previous works in the field.
The scaling of IC feature sizes has increased the integration capability and allowed the design of large systems in one single chip. This improvement has also contributed to reconfigurable circuits densities, such as the Xilinx Virtex-4 FPGA, which exceeds ten million gates. In spite of that, circuit miniaturization will also increase defect and fault rates in such high magnitude that a fault tolerance...
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