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Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
Welcome to the 20th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) in Santa Cruz, California. VLSI-SoC was inaugurated 30 years ago and has been held 20 times in numerous international cities. The diverse and rich set of locations parallel the diverse and rich set of participants. The previous conference locations have included: Edinburgh, Scotland (1981); Trondheim,...
The safety of electrode-tissue interface under electrical neural stimulation is a critical matter and thus precise control of the electrode voltage needs to be warranted. Analytical study on the electrode potential profile during electrical stimulation justifies the need of using a closed-loop system to regulate the electrode voltage. A neural stimulator with cancellation of excessive charge is proposed...
We introduce a Force-directed List Scheduling (FDLS) algorithm for resource-constrained assay compilation targeting Digital Microfluidic Biochips (DMFBs). This algorithm has been used in the past for high-level synthesis of digital signal processing systems, and is now applied to DMFB synthesis. The results show improvements compared to List Scheduling (LS) and Path Scheduling (PS), the most efficient...
This paper describes the design of a low-noise amplifier for ultrasound receiver application. The receiver consists of a transimpedance amplifier (TIA) followed by a current feedback amplifier (CFA) and an output buffer stage to drive a 75Ω coaxial cable. The design is optimized in terms of noise and bandwidth for capacitive micromachined ultrasonic transducer (CMUT). Amplifier design issues such...
3D die stacking integration technology offers a feasible and promising solution to overcome the barriers of interconnect efficiency and device scaling in modern systems. The emerging trend from 2D IC to 3D IC obtains better performance by getting more silicon area and shortening wire length. In 3D integration technologies, different layers of active devices are connected through vertical links. Currently,...
The use of embedded fault-tolerant mechanisms in Network-on-Chips (NoCs) has become essential to ensure connectivity in the presence of massive defects, and consequently improving the yield. According to the number of defects and their location in NoC, the fault tolerant techniques can be very expensive in terms of area, performance and energy overhead. The use of testing and diagnosis can help to...
Shared L1 memories are of interest for tightly-coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depends on the architecture of the low-latency interconnect between processors and memory banks, which needs to provide ultra-fast access to the largest...
The new generation of Power Management Controller (PMC) for Microcontroller Units (MCU) in the automotive application field is targeting increased modularity and flexibility of use, aiming to simplify board design and reduce external components as well as to reduce both development time and high volume production cost. A structural PMC design approach is followed by breaking the Intellectual Property...
This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive...
This paper describes the design of a switched-capacitor fourth-order single-loop ΣΔ modulator with a 5-level embedded quantizer. The loop filter consists of a cascade of resonators with distributed feedforward coefficients, which can be programmed to make the zeros of the noise transfer function variable. As a result, the modulator can be reconfigured either as a lowpass or as a bandpass analog-to-digital...
A novel double floating-gate unified memory device is experimentally demonstrated for the first time. The device can be used to store both volatile and nonvolatile memory states simultaneously. Simulations of scaled devices show that the device offers several advantages compared to conventional memory devices. Such a device could have a dramatic impact on next generation memory architectures.
Distributed inductor-capacitor (LC) resonant clocking is a recent, promising technique to reduce the energy consumption in Clock Distribution Networks (CDNs) by recycling the energy on-chip. Even though the majority of power is saved, resonant clocks distribute a sinusoidal clock signal with a 25% slew which increases short-circuit power in the sequential elements compared to traditional buffered...
Channel estimation is a crucial task for the overall communication performance of a wireless receiver. Compared to traditional approaches the estimation of the wireless channel can be improved by using iterative estimation with feedback from other receiver components, however the VLSI implementation of such iterative channel estimation in multiple-input multiple-output (MIMO) orthogonal frequency...
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