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Split-path data driven dynamic logic (SPD3L) is used wherever low power design is desired. It uses subset of input signals instead of global clock to maintain the correct pre-charge and evaluation phases. Elimination of clock network results in substantial reduction in power dissipation compared to dynamic domino logic. In this work, two 6×6 booth multipliers are implemented in 1.8V 0.18um CMOS technology,...
In Multi-VDD system, Level Converter (LC) is used to convert one voltage level to another level (i.e. high to low and low to high). Power gating is an approach to reduce the dynamic and standby leakage in the present day System on Chip (SoC) design. As we go lower down the technology node problem of ground bouncing starts to dominate the system. It leads to various kinds of errors especially the functional...
Top contact organic thin-film field effect transistors based on regioregular poly(3-butylthiophene-2,5-diyl) (P3BT), poly(3-dodecylthiophene-2,5-diyl) (P3DDT) and poly(3-hexylthiophene-2,5-diyl) (P3HT) of similar concentration were fabricated by spin coating technique. The current-voltage (I-V) characteristics of these three different polymer based organic field-effect transistors (OFETs) were studied...
Clock Distribution has played a key role in designing the synchronous systems. Even with the systems moving towards Globally Asynchronous and Locally Synchronous (GALS) a need for low power clock distribution network exists as it consumes a major portion of the circuit power. In this paper we demonstrate the effect of various level converters on clock distribution networks. Also we propose a novel...
The power gating is a technique to reduce leakage power in standby mode by using Sleep switch. In power gating, the circuit suffers the ground bouncing due to the switching of the Sleep Transistor from standby mode to active mode. In this paper, we have presented a four step power gating technique for further reducing the Ground/Power bouncing. This technique not only controls the bouncing but also...
An organic thin film transistor (OTFT) based on chemically synthesized poly-3-hexylthiophene (P3HT) is successfully fabricated and I–V characteristics of the device is measured at room temperature. The key performance parameters such as ON/OFF ratio, threshold voltage, carrier mobility, conductivity and transconductance are extracted through the I–V characteristics of OTFT and discussed in the paper.
This paper discusses a new method of hiding ASCII characters into still cover image. It is based on finding match between the bit of the randomly selected image pixel and the data bits. Higher nibbles are used for data hiding at a position indicated in the lower nibble using a 2-bit code word. Simulation results on IEEE standard Lena image hiding 800 ASCII text characters are given. It is shown that...
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