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In this work, the influence of back biasing on the effective mobility in Ultra Thin film and ultra thin Box Fully Depleted SOI devices is studied. The evolution of the carrier mobility with the effective field on large N & PMOS devices for thin (GO1) and thick gate oxide (GO2) is investigated. The impact of surface roughness scattering at high electric on the effective mobility is also demonstrated...
This paper highlights the interest of FD-SOI with high-k and metal gate as a possible candidate for low power multimedia technology. The possibility of multi-VT by combining UTBOX with back plane, back biasing, variable TiN thickness and Al2O3 in the gate stack is demonstrated. The viability of these approaches is corroborated via mobility and reliability measurements. Dual gate oxide co-integrated...
Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate is sufficient to provide a high symmetrical...
Gate-to-channel capacitance Cgc(Vg) data obtained on FD-SOI MOS devices with gate lengths down to 35nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and Box capacitances...
In this paper, we demonstrate high performance Fully Depleted Silicon-On-Insulator CMOS on 300mm strained SOI (sSOI) wafers. Up to 100% drive current (ION) enhancement is demonstrated by sSOI nMOSFETs vs. unstrained SOI at W=80nm active width and L=45nm gate length. These devices indeed yield 1200μA/μm ION at IOFF=10-8 A/μm and VD=0.9V supply voltage. At the same time, they highlight the same excellent...
In this paper, a new ultra-thin body and BOX (UT2B) fully-depleted (FD) silicon-on-insulator (SOI) device architecture based on a stacked back plane (BP) and WELL below the BOX is presented. The proposed device has been developed to boost the gate-to-channel electrostatic control and to be compatible with the adaptive body biasing (ABB) techniques for low power applications. The concept viability...
For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve ION current improvement by 45% for LVT options at an IOFF current of 23nA/μm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um2 bitcells with 290mV SNM at 1.1V and Vb=0V operation...
This paper highlights the successful co-integration of Localized Silicon-On-Insulator (LSOI) devices and of bulk-Si I/O devices on the same chip. LSOI devices present good logic performances and very low mismatch values down to 1.2mV/μm. In addition, we show the backbiasing impact on LSOI SRAM bit-cells for stability improvement. This work also presents the co-integration of LSOI with bulk devices...
We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow improving the electrostatic control (and in turn the dynamic performance by 22%) and the variability of Complementary Metal-Oxide-Semiconductors (CMOS) devices, compared to the bulk technology. It is thus an ideal solution for Low Power (LP) applications and SRAM stability at the 22 nm node and below. Moreover,...
A low-cost and high-manufacturability Multi-VT Ultra-Thin BOX and Body (UT2B) FDSOI technology is proposed for high-performance and low-leakage digital circuits. This concept allows setting up low, standard and high threshold voltage (VT) devices without degrading the good channel electrostatic control and the low VT dispersion of the FDSOI technology. Device electrical characteristics, process flow...
In this paper the modelling approaches for determination of the drain current in nanoscale MOSFETs pursued by various partners in the frame of the European Projects Pullnano and Nanosil are mutually compared in terms of drain current and internal quantities (average velocity and inversion charge). The comparison has been carried out by simulating template devices representative of 22 nm Double-Gate...
The objective of this paper is to present the successful co-integration of Logic Ultra-Thin Body and Box (UTBB) devices and bulk-Si I/O devices on the same chip. The UTBB transistors are integrated locally on a Bulk wafer with the Localized Silicon On Insulator (LSOI) process technology with HfO2/TiN gate stack for low power applications. I/O co-integrated Bulk devices have a thicker interfacial SiO...
We investigate the influence of different technological parameters on ESD robustness in advanced FDSOI devices. From Transmission Line Pulse (TLP) measurements, a comparison with other technologies enables us to evaluate the impact of ultrathin film and buried oxide. A solution based on hybrid SOI/bulk co-integration by using Silicon-On-Nothing technology is presented in order to improve ultra-thin...
In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17 ??/Vdd 1.1 V and 29 ??/Vdd 1.8 V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators...
In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and...
In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and...
In this paper, an original and simple concept for setting up multi-VT for fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs is presented. Low, standard and high threshold voltage (VT) devices are achieved without degrading the good channel electrostatic control and the low VT dispersion of the FDSOI technology. The concept is based on the use of a thin buried oxide (BOx) combined with the integration...
The mobility and, more generally, the transport parameters of MOS devices are key quantities for the performance evaluation in advanced CMOS technologies. In this work, a review of the main mobility results obtained in short channel devices (here GAA/DG, FD-SOI MOSFETs and FinFETs) are presented and discussed for better understanding their transport limitations and, in turn, their performances.
In this paper, a new compact, robust and low leakage 4T SRAM cell is proposed. It is based on an original concept of multi-VT thin buried oxide (BOx) fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs with ground plane (GP) in 45 nm technology node. The stability of the cell reaches 20% of VDD and the cell leakage is 13 pA. A minimum cell area of 0.209 mum2 with specific 45 nm SRAM design rules...
Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO2 or HfSiON) and Si/SiO2 interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier...
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