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In this paper, we show the process and integration results of small TSVs integrated by 300mm 3DIC BTSV process. The TSV size is from 2um to 3um (in diameter) with aspect ratio of 10. The achievements of this work are: 1) successful demonstration of 20um thin wafer process by ITRI's 300mm wafer thinning process; 2) 2∼3um TSV patterning and etching performed by backside TSV process; 3) Combination of...
Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical...
Low-cost 3DIC process approaches are investigated in terms of 3D stacking method and TSV process integration scheme. The permanent and bumpless wafer-to-wafer (PBWW) bonding technology can be applied to the DRAM wafers in the wide-I/O memory cube application. Backside TSV process with its electrical characteristics is also studied. The combination of these two process technologies can further lower...
An adequate sequential etching though dielectrics, silicon and permanent adhesive material was successfully developed for the damascene interconnects in the face-to-back bumpless TSV Wafer on Wafer (WOW) processes. The induced bowing taken place at the etching of permanent adhesive was optimized and no void Cu metallization was achieved. According to those TSV technology, the upper and lower stacked...
Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3DIC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame...
TSVs (through-silicon vias) can be fabricated by the via-first, via-middle, and via-last from the backside processes. For via-first and via-middle processes, TSVs are formed from the frontside of the wafer which is temporary bonded to a carrier. Then the backside is subjected to backgrinding and Cu revealing such as silicon dry etching, low-temperature isolation SiN/SiO2 deposition, and CMP (chemical-mechanical...
A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of...
Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate...
TSV (through silicon via) metallization is one key process in 3DIC integration. Due to high aspect ratio and filling volume, TSV copper plating is the most time-consuming module in the whole process flow. To increase the throughput of electroplating, tool configurations and plating chemistry should be optimized. In this work, an electroplating chamber with a novel paddle design is used in this experiment...
In this study, the design, fabrication, and calibration of the piezoresistive stress sensors [1–18] embedded in a TSV (through silicon via) interposer in a 300mm wafer are investigated. The results presented herein should be useful for the development of 3D integration such as measuring the strength of the TSV device and interposer wafers, during and after all the processes such as wafer thinning,...
Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules...
In this paper, the optimization of Cu chemical-mechanical polishing (CMP) performance (dishing) for the removal of thick Cu-plating overburden due to Cu plating for deep through silicon via (TSV) in a 300-mm wafer is investigated. Moreover, backside isolation oxide CMP for TSV Cu exposure is examined. To obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for...
This paper demonstrates an effective TSV test-key and the coupled measurement method to determine TSVs' (through-silicon vias) thermal integrity before wafer thinning by using a thermal measuring technique. The test-key comprises two linear metallic traces with the same shape which are deposited on a silicon wafer: one coupled with a line of embedded blind vias, the other coupled without any via....
The effects of etch rate on TSV sidewall variation in 8” (200mm) and 12” (300mm) wafers are investigated in this study. Emphasis is placed on the determination of sidewall scallop with different etch rates ranging from 1.7μm/min to 18μm/min and various TSV diameters (1μm, 10μm, 20μm, 30μm, and 50μm) by design of experiments (DoE). The BHE in/out (2666Pa/2666Pa) are the same for all the cases. Also,...
A comprehensive investigation for the structural and electrical influences of via-last through silicon via (TSV) process on the 0.18-μm MOSFETs has been proposed in this work. The well-isolated TSVs don't affect the threshold voltages and drain currents in terms of the MOSFET distances to the TSVs, the size of the TSVs, the configuration of TSVs, and the positions of MOSFETs by the TSVs. Over-wafer...
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