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Process issues and challenges of three-dimensional integrated circuit (3DIC) using through-silicon-via (TSV) are extensively investigated. Key enabling process technologies in the TSV formation and thin wafer handling are discussed with a viewpoint of TSV process integration. Test element groups (TEG) are designed to characterize the process performance and optimizations of some key process modules...
In this paper, the optimization of Cu chemical-mechanical polishing (CMP) performance (dishing) for the removal of thick Cu-plating overburden due to Cu plating for deep through silicon via (TSV) in a 300-mm wafer is investigated. Moreover, backside isolation oxide CMP for TSV Cu exposure is examined. To obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for...
The effects of etch rate on TSV sidewall variation in 8” (200mm) and 12” (300mm) wafers are investigated in this study. Emphasis is placed on the determination of sidewall scallop with different etch rates ranging from 1.7μm/min to 18μm/min and various TSV diameters (1μm, 10μm, 20μm, 30μm, and 50μm) by design of experiments (DoE). The BHE in/out (2666Pa/2666Pa) are the same for all the cases. Also,...
A comprehensive investigation for the structural and electrical influences of via-last through silicon via (TSV) process on the 0.18-μm MOSFETs has been proposed in this work. The well-isolated TSVs don't affect the threshold voltages and drain currents in terms of the MOSFET distances to the TSVs, the size of the TSVs, the configuration of TSVs, and the positions of MOSFETs by the TSVs. Over-wafer...
In this paper, we present a 0.8-μm 1P2M CMOS process compatible polysilicon/titanium thermopile with a gold black absorption layer. Instead of an aluminum layer of 0.6 μm thickness in the first metallization process, a titanium layer of 0.1 μm thickness was introduced to the fabrication of a CMOS compatible thermopile in order to enhance sensitivity by lowering the thermal conductance of the sensor...
Suspended structures are frequently used in some micro-electro-mechanical system (MEMS) devices. They are usually protected and supported by silicon oxide. Because the suspended structures are released from the silicon substrate in various etchants, the etch resistivity of the oxide layer is very important for suspended structure fabrication. In this paper, we improve the etch resistivity of low temperature...
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