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Fault simulation is a critical tool in design, analysis of testability and verification of circuits. BDDs are a well-known model for manipulating Boolean functions. We propose a new type of BDD in the form of Shared Structurally Synthesized BDD (S3BDD) for representing the structure and simulating of faults in digital circuits. The paper offers a formula for calculating the minimal size, a method...
The paper presents a new structural fault collapsing method with linear algorithmic complexity to reduce the search space for test generation and fault diagnosis in digital circuits. The method is based on the two phase topology analysis of the circuit description. The first phase of fault collapsing is carried out on the gate level during superposition of Binary Decision Diagrams (BDD) of logic gates,...
A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented for modeling sequential circuits for fault simulation purposes. The size of S BDD is in linear correlation with the circuit size and is characterized by the property of one-to-one mapping between the nodes in the graph and signal paths in the corresponding sequential circuit. A method is proposed for synthesis of...
A new method for logic simulation and fault modeling in combinational circuits with Structurally Synthesized BDDs (SSBDD) is proposed. The new model is constructed by merging different super-graphs (SSBDDs) related to different circuit outputs, which share as much as possible different subgraphs (SSBDDs) representing the circuit. We call this model as Shared SSBDDs (S3BDD) where each node represents...
In this paper we present two methods for synthesis of High-Level Decision Diagrams (HLDD) for representing digital systems at higher behavior, functional or register-transfer levels. The first method is based on symbolic execution of procedural descriptions, which corresponds to functional representation of systems on the behavioral level. The second one is based on iterative superposition of HLDDs,...
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