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A 6-bits 6-GS/s flash ADC is presented. Single-stage integrators are proposed as preamplifiers to drive the comparators. Compared to single-stage voltage amplifiers, integrators limit the gain-bandwidth requirements leading to lower power dissipation and smaller device size. Comparators are inter-leaved and clocked at half rate, limiting dissipation thanks to the longer available regeneration time...
A 45 nm CMOS receiver based on an unclocked DFE is presented. A bi-dimensional equalization simultaneously adapts the DFE tap value and feedback delay, optimizing both the vertical and horizontal eye opening at the sampler input. Realized prototypes show error free operation at 12 Gb/s with 39 dB backplane loss. The receiver core occupies 0.1 mm2 and consumes 130 mW.
In this paper we present a reconfigurable Class-E Power Amplifier (PA) whose operation frequency covers all uplink bands of GSM standard. We describe the circuit design strategy to reconfigure PA operation frequency maximizing the efficiency. Two dies, manufactured using CMOS and MEMS technologies, are assembled through bondwires in a SiP fashion. Prototypes deliver 20dBm output power with 38% and...
In this work we present a reconfigurable mid-power class-E power amplifier (PA) operating at ~900 MHz and ~1800 MHz (GSM standard) realized hybridizing one chip manufactured in AMS 0.35 mum CMOS technology and one MEMS sub-network. The CMOS chip realizes the active part of the circuit, whereas the MEMS block (realized in FBK technology) implements a reconfigurable impedance matching network (MN) that...
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