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Dynamically Reconfigurable Systems (DRS), which allow logic to be partially reconfigured during run-time, are promising candidates for embedded and high-performance systems. However, their architectural flexibility introduces a new dimension to the functional verification problem. Dynamic reconfiguration requires the designer to consider new issues such as synchronizing, isolating and initializing...
Restoring sight to the visually impaired poses significant challenges across multiple disciplines. In this demonstration, we present a prototype vision processing system to perform the external processing and to provide a technical user interface for a vision prosthesis. The system transforms an input video stream into intensity values suitable for transmission to a stimulation array implanted within...
Application circuits configured on Xilinx Virtex series FPGAs are able to reconfigure the FPGA at run time using the on-chip ICAP. Traditional methods of accessing the ICAP using OPB-based and PLB-based schemes are unnecessarily complex and rarely reused. In this study, a new interface for accessing the ICAP is introduced. The interface is easy to use, it can readily be integrated to different systems,...
This paper presents a complete design of a reconfigurable architecture support system, called ACS (an addressless configuration support), which provides efficient access to non-contiguous reconfigurable locations in reconfigurable systems. ACS reduces the amount of partial reconfiguration information required by removing a large amount of addressing information and padding as found in Virtex-4 bitstreams...
Communications infrastructure for modular reconfiguration of FPGAs needs to support the changing communications interfaces of a sequence of modules. In order to avoid the overheads incurred by a bus system or network-on-chip, the approach we have taken is to create point-to-point wiring harnesses to support the dynamic intermodule communications. These harnesses are reconfigured at various stages...
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel method to reduce reconfiguration time by maximising wire use and minimising wire reconfiguration. This builds upon our previously-presented methodology for creating modular, dynamically-reconfigurable applications targeted...
In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family. We demonstrate that simple off-the-shelf compression...
We present a hardware implementation of population-based ant colony optimization (P-ACO) on field-programmable gate arrays (FPGAs). The ant colony optimization meta-heuristic is adopted from the natural foraging behavior of real ants and has been used to find good solutions to a wide spectrum of combinatorial optimization problems. We describe the P-ACO algorithm and present a circuit architecture...
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