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One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the threshold voltage of pMOS transistors, which slows down signal propagation along the paths between flip-flops. As a consequence, NBTI may cause transient faults and, ultimately, permanent circuit functional failure. In this paper, we propose...
The paper proposes a method for locating design errors at the source-level of hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models. The method is based on backtracing the mismatched and matched outputs of the system under verification on HLDDs. Experiments on a set of sequential register-transfer level benchmarks show that the method is capable...
The paper proposes high-level decision diagrams (HLDDs) model based structural coverage metrics that are applicable to both verification and high-level test. Previous works have shown that HLDDs are an efficient model for simulation and test generation. However, the coverage properties of HLDDs against hardware description languages (HDL) have not been studied in detail before. In this paper we show...
The efficiency of test generation (quality, speed) for digital systems like microprocessors is highly depending on the methods for diagnostic modeling of systems. For systems with high logic complexity higher level methods are unavoidable.A method is discussed for modeling microprocessors with high level Decision Diagrams (DD). DDs can be used for developing a general theory for diagnosis of systems...
Assertions have proven to be an effective mechanism to improve quality and to speed-up simulation-based design verification. They are created and embedded to the simulatable design description by the designer, the person with the deepest knowledge about the desired functionality and its real implementation. In this paper we propose to reuse this valuable information during the design manufacturing...
Previous works have shown that high-level decision diagrams (HLDD-s) are suitable for system representation for analyzing code coverage metrics. This is due to the fact that HLDD models implicitly represent classical code coverage items, such as statement and branch coverage. However, research on the properties of HLDD-s, which contribute to the accuracy of coverage assessment, is missing. Current...
Current paper proposes a new hierarchical approach to defect-oriented testing of CMOS circuits. The method is based on critical area extraction for identifying the possible shorted pairs of nets on the basis of the chip layout information, combined with logic-level test pattern generation. The novel contributions of the paper are a new bridging fault simulator and a test pattern generator, which are...
The paper presents a new framework for digital systems verification. The framework has been developed in Tallinn University of Technology and it is called APRICOT. It supports a wide range of verification tasks including assertion checking, code coverage analysis, simulation, test generation and property checking and it is also easy to set up and use. Therefore it is highly suitable for supporting...
The paper proposes a novel method for PSL language assertions simulation-based checking. The method uses a system representation model called High-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal...
The paper proposes a novel method of analyzing code coverage metrics on a system representation called high-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and test pattern generation. Current paper presents a technique, where fast HLDD based simulation is extended to support seamless code coverage analysis. We show how classical code coverage...
In this paper, a new hierarchical multi-level technique for malicious fault list generation for evaluating the fault tolerance is presented. For the description of the system three levels are exploited: behavioral, functional signal path and structural gate-network levels, whereas at each level the model of decision diagrams and uniform fault analysis procedures are used. Malicious faults are found...
As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeting these defects, such as the bridging fault test pattern generators have been available for a long time. However, this paper proposes a new hierarchical approach based on critical area extraction for identifying the possible...
The paper presents a new tool called TTBist for DfT synthesis of IP cores in systems-on-a-chip. While scan-based approaches have been known for a long time, they have shortcomings and they are rarely used in practice in smaller design companies. The current paper introduces a new alternative for this traditional method. The tool TTBist allows to automatically insert built-in self-test (BIST) structures...
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