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This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below −80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase...
This paper describes a fully integrated scalable discrete-time receiver based on a merged SC mixer, filter and SAR ADC meeting the requirements of IEEE 802.16e and 802.11b/g/n standards. Recent work has shown the use of SC-filtering techniques in radio receivers, where sampling is done early in the RX path. Such discrete-time architectures require an early anti-aliasing (AA) filter prior to sampling...
This work demonstrates the feasibility of a distributed voltage controlled oscillator (DVCO) designed for WLAN applications in a 65 nm CMOS process with standard VLSI backend. This DVCO achieves a tuning range of 1.1 GHz (from 10.6 GHz to 11.7 GHz) and a measured phase noise of -116 dBc/Hz at 1 MHz offset from the carrier. To achieve such performances, the DVCO consumes a DC current of 36 mA from...
This paper summarizes the electrical characterization of MIM capacitor realized in three dimensions. Manufacturing of the device is described, as well as an electrical comparison of three dielectrics, Si3N4, Al2O3, Ta2O5 and two deposition methods, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Selecting Al2O3 deposited by ALD, high density of 35 nF/mm2 is obtained...
This paper summarizes the electrical characterization of MIM capacitor realized in three-dimensional. High density of 35nF/mm2 is obtained with low leakage current. Its integration in BiCMOS technology is demonstrated and three circuits are characterized
This paper presents the design of a distributed voltage controlled oscillator (DVCO). This oscillator has been designed in a low-cost low-power standard STMicroelectronics 65nm CMOS process. The DVCO achieves a tuning range from 9.6GHz to 11.6GHz, a phase noise better than -101dBc/Hz at 1MHz offset from the carrier and a total power consumption of 29mW
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