Search results for: U. Singisetti

Items from 1 to 18 out of 18 results

article

Enhancement-Mode N-Polar GaN MISFETs With Self-Aligned Source/Drain Regrowth

U Singisetti, Man Hoi Wong, S Dasgupta, Nidhi, more

IEEE Electron Device Letters > 2011 > 32 > 2 > 137 - 139

We report gate-first enhancement-mode (E-mode) N-polar GaN MISFET devices with self-aligned source/drain regions by molecular beam epitaxy regrowth and with a SiNx gate dielectric. E-mode operation at V_ds = 4.0 V is demonstrated for devices with gate lengths >; 0.18 μm with a 20-nm GaN channel and a high-temperature SiNx gate dielectric. A high drain current of 0.74 A/mm was measured for an Lg...

article

Self-Aligned Technology for N-Polar GaN/Al(Ga)N MIS-HEMTs

Nidhi, S Dasgupta, D F Brown, U Singisetti, more

IEEE Electron Device Letters > 2011 > 32 > 1 > 33 - 35

In this letter, we introduce a scalable self-aligned technology for N-polar GaN MIS-HEMTs which can be used to achieve significant improvement in device performance by minimizing the source and drain access resistances. The methodology consists of a refractory-metal gate-first process followed by the regrowth of polarization-doped graded InGaN and InN layers by plasma-assisted molecular-beam epitaxy...

chapter

III-V MOSFETs: Scaling laws, scaling limits, fabrication processes

M J W Rodwell, U Singisetti, M Wistey, G J Burek, more

2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM) > 1 - 6

2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM 2010)

III-V FETs are in development for both THz and VLSI applications. In VLSI, high drive currents are sought at low gate drive voltages, while in THz circuits, high cutoff frequencies are required. In both cases, source and drain access resistivities must be decreased, and transconductance and drain current per unit gate width must be increased by reducing the gate dielectric thickness, reducing the...

chapter

0.37 mS/μm In_0.53Ga_0.47As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain

U. Singisetti, M.A. Wistey, G.J. Burek, A.K. Baraskar, more

2009 Device Research Conference > 253 - 254

2009 67th Annual Device Research Conference (DRC)

InGaAs has been extensively studied as a potential channel material for sub-22nm gate length VLSI MOSFETs because of its low electron effective mass (m ) hence high electron velocity (v). At sub-22 nm gate lengths, a maximum 1 nm EOT dielectric and 5 nm thick channel with strong vertical confinement are required for high subthreshold slope and acceptably low drain induced barrier lowering (DIBL)....

chapter

Effect of surface preparations on contact resistivity of TiW to highly doped n-InGaAs

V. Jain, A.K. Baraskar, M.A. Wistey, U. Singisetti, more

2009 IEEE International Conference on Indium Phosphide&Related Materials > 358 - 361

2009 IEEE International Conference on Indium Phosphide & Related Materials

We report the effects of UV-ozone oxidation, oxide removal etch chemistry (dilute HCl or concentrated NH₄OH), semiconductor doping, and annealing on the contact resistivity (rho_c) of Ti_0.1W_0.9 refractory alloy to n-type InGaAs. The semiconductor surface was oxidized through exposure to UV-ozone, then subsequently etched by either dilute HCl or concentrated NH₄OH before TiW contacts were deposited...

chapter

Enhancement mode In0.53Ga0.47As MOSFET with self-aligned epitaxial source/drain regrowth

U. Singisetti, M.A. Wistey, G.J. Burek, A.K. Baraskar, more

2009 IEEE International Conference on Indium Phosphide&Related Materials > 120 - 123

2009 IEEE International Conference on Indium Phosphide & Related Materials

A scalable, self-aligned In_0.53Ga_0.47As MOSFET process was developed and enhancement mode device operation was demonstrated. The 0.7 mum L_g device shows a maximum drive current of 0.14 mA/mum at V_gs=4.0 V and V_ds=2.5 V. The devices have almost an order of magnitude larger drive current than our previously reported MOSFETs. The channel layer was 5 nm thick InGaAs with InAlAs bottom barrier for vertical...

article

Height-selective etching for regrowth of self-aligned contacts using MBE

G.J. Burek, M.A. Wistey, U. Singisetti, A. Nelson, more

Journal of Crystal Growth > 2009 > 311 > 7 > 1984-1987

Advanced III–V transistors require unprecedented low-resistance contacts in order to simultaneously scale bandwidth, f _max and f _t with the physical active region [M.J.W. Rodwell, M. Le, B. Brar, in: Proceedings of the IEEE, 96, 2008, p. 748]. Low-resistance contacts have been previously demonstrated using molecular beam epitaxy (MBE), which provides active doping above 4×10 ¹⁹...

article

$\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Channel <emphasis emphasistype="roman">MOSFETs</emphasis> With Self-Aligned <emphasis emphasistype="roman">InAs</emphasis> Source/Drain Formed by MEE Regrowth

U. Singisetti, M.A. Wistey, G.J. Burek, A.K. Baraskar, more

IEEE Electron Device Letters > 2009 > 30 > 11 > 1128 - 1130

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below...

chapter

Technology development & design for 22 nm InGaAs/InP-channel MOSFETs

M. J. W. Rodwell, M. Wistey, U. Singisetti, G. Burek, more

2008 20th International Conference on Indium Phosphide and Related Materials > 1 - 6

2008 IEEE 20th International Conference on Indium Phosphide & Related Materials (IPRM)

Because of the low electron effective mass and the high resulting carrier velocities, we are developing InGaAs/InP MOSFETs for potential application in VLSI circuits at scaling generations beyond 22 nm. We will report device design, review gate dielectric growth processes, and describe in detail the development of process modules for fabrication of fully self-aligned enhancement-mode devices. Key...

chapter

Technology development & design for 22 nm InGaAs/InP-channel MOSFETs

M. Rodwell, M. Wistey, U. Singisetti, G. Burek, more

2008 20th International Conference on Indium Phosphide and Related Materials > 1 - 6

2008 IEEE 20th International Conference on Indium Phosphide & Related Materials (IPRM)

chapter

On the Feasibility of few-THz Bipolar Transistors

M. Rodwell, E. Lind, Z. Griffith, A.M. Crook, more

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting > 17 - 21

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

We review the limits faced in seating of InP-based bipolar transistors for increased device bandwidth. Emitter and base contact resistivities and IC thermal resistance are the major limits to increased device bandwidth. Devices with 1-1.5 THz simultaneous f_tau, and f_max are feasible; these will enable 750 GHz monolithic amplifiers and medium-scale digital ICs at ~400-500 GHz clock rate.

chapter

Ultra-Low Resistance Ohmic Contacts to InGaAs/InP

U. Singisetti, A. M. Crook, E. Lind, J. D. Zimmerman, more

2007 65th Annual Device Research Conference > 149 - 150

65th Device Research Conference

chapter

Frequency Limits of InP-based Integrated Circuits

Mark Rodwell, E. Lind, Z. Griffith, S. R. Bank, more

2007 IEEE 19th International Conference on Indium Phosphide&Related Materials > 9 - 13

2007 International Conference on Indium Phosphide and Related Materials

We examine the limits in scaling of InP-based bipolar and field effect transistors for increased device bandwidth. With InP-based HBTs, emitter and base contact resistivities and IC thermal resistance are the major limits to increased device bandwidth; devices with 1-1.5 THz simultaneous f? and fmax are feasible. Major challenges faced in developing either InGaAs HEMTs having THz cutoff frequencies...

chapter

Developing Bipolar Transistors for Sub-mm-Wave Amplifiers and Next-Generation (300 GHz) Digital Circuits

Mark Rodwell, Z. Griffith, N. Parthasarathy, E. Lind, more

2006 64th Device Research Conference > 5 - 8

2006 64th Device Research Conference

chapter

Frequency Limits of Bipolar Integrated Circuits

M. Rodwell, Z. Griffith, N. Parthasarathy, U. Singisetti, more

2006 IEEE MTT-S International Microwave Symposium Digest > 329 - 332

2006 IEEE MTT-S International Microwave Symposium Digest

InP HBTs at the 500 nm scaling generation have attained 450 GHz balanced cutoff frequencies and ~4 V breakdown. With such devices, 150 GHz digital circuits (static dividers) have been demonstrated. 175 GHz amplifiers have been demonstrated with slower HBTs. We discuss transistor scaling laws and scaling limits for realizing digital and analog/RF circuits at sub-mm-wave frequencies; the most critical...

chapter

Selectively Implanted Subcollector DHBTs

N. Parthasarathy, Z. Griffith, C. Kadow, U. Singisetti, more

2006 International Conference on Indium Phosphide and Related Materials Conference Proceedings > 104 - 107

2006 International Conference on Indium Phosphide and Related Materials Conference Proceedings

In_0.53Ga_0.47As/InP double heterojunction bipolar transistors with implanted subcollectors have been designed and fabricated to eliminate the base access pad capacitance. A blanket Fe implant eliminates the interface charge and a patterned Si implant creates an isolated N⁺⁺ subcollector. The extrinsic base-collector capacitance C_cb associated with the base interconnect pad (-25% of the total C_cb) is...

article

Two-dimensional electrical characterization of ultrashallow source/drain extensions for nanoscale MOSFETs

U. Singisetti, M.R. McCartney, J. Li, P.S. Chakraborty, more

Superlattices and Microstructures > 2003 > 34 > 3-6 > 301-310

State-of-the-art semiconductor devices require accurate control of the full two-dimensional dopant distribution. In this work, we report results obtained on 2D electrical characterization of ultra shallow junctions in Si using off axis electron holography to study two-dimensional effects on diffusion. In particular, the effect of a nitride diffusion mask on lateral diffusion of phosphorous is discussed...

article

Electron holographic characterization of nanoscale charge distributions for ultra shallow PN junctions in Si

P.S. Chakraborty, M.R. McCartney, J. Li, C. Gopalan, more

Physica E: Low-dimensional Systems and Nanostructures > 2003 > 19 > 1-2 > 167-172

This study extends electron holography as a quantitative characterization tool for nanoscale charge distributions associated with ultra shallow PN junctions in Si, which are needed for fabricating nanoscale MOSFETs, Si quantum dots and single electron transistors. The ultra shallow junctions were fabricated using rapid thermal diffusion from a heavily doped n-type surface source onto a heavily doped...

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