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Large-scale graph processing is now a crucial task of many commercial applications, and it is conventionally supported by general-purpose processors. These processors are designed to flexibly support highly diverse workloads with classic techniques such as on-chip cache and dynamic pipelining. Yet, it is difficult for the on-chip cache to exploit irregular data locality in large-scale graph processing,...
Aiming at related task scheduling in cloud computing, a cost-effective precedence constrained tasks scheduling algorithm is presented. The algorithm takes into account the monetary cost and tries to fulfill a task scheduling balancing time and cost. In order to explore more possible solutions with high quality ignored by the deterministic algorithm, multi-population genetic algorithm is adopted to...
A new simple maskless fabrication method based on room temperature Bosh process was developed to fabricate silicon nanoforest. After being coated with a layer of Au, the Au-coated silicon nanoforest was converted into a surface-enhanced Raman spectroscopy (SERS) substrate. To further enhance SERS signals, the Au-coated silicon nanoforest was grafted with silver-plate nanoparticles (AgNPs). The SERS...
It is demonstrated that the high quality factor of thick metal spiral inductors and passive circuits with low induced harmonics power level can be achieved by using a mature glass substrate technology. It is very critical and helpful with lower harmonic power level for the FEM development of current and next generation's commercial 4G carrier aggregation system.
According to the analysis of substrate integrated waveguide structure, a design of double-layer and seven-order MEMS bandpass filter using network synthesis is proposed in this paper. The simulation and optimization are explained with Ansoft HFSS. Based on MEMS technology, a millimeter-wave filter is designed with a center frequency at 30GHz, the 1dB bandwidth range is 690MHz, the passband return...
A high efficient CMOS class-E power amplifier (PA) by using Quad Flat No-leads (QFN) package combined with Through Silicon Via (TSV) grounding is presented. TSV has much smaller parasitic inductance and resistance than wire-bonds. TSV technology can improve PA efficiency, reduce die size samples and retain low cost in QFN package. The TSV samples are made and measured by using double-side probing...
In this paper, results of twisted pairs implemented in silicon IPD and low loss MLO up to 20 GHz is reported. First, origin of differential lines is explained, followed by explanation of differential twisted pairs' natural ability to suppress noise. Issues related to differential twisted pairs (DTPs) are also discussed. In this paper, differential lines with and without (i.e., the coupled lines) twists...
In this paper, the performance of GSG co-planar waveguide (CPW) type transmission line on silicon interposer and stacking memories by through-silicon-vias (TSVs) are analyzed. The high conductor loss of fine lines will cause the impedance varying with frequency and make the reflection loss minor. Furthermore the flat attenuation of such fine line will result in low distortion waveforms and have better...
Most of the MEMS inertial switches developed in recent years are intended for shock and impact sensing above 40 g. These switches are fabricated based on non-silicon surface micromachining with multiple steps of electroplating. In this paper, a silicon based low-g inertial switch typically used for linear acceleration sensing is designed and fabricated. The inertial switch consists of a high volume...
In this paper, the package solutions for die-to-die interconnection including fine-line substrate and ASE advance wafer level package (aWLP) have been purposed. The fin-line substrate has 3um trace width and 3um trace space on top layer with copper interconnection. For aWLP, the trace width and space of interconnection on redistribution layer (RDL) is the same with fine-line substrate. The different...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
To realize the reliability of a high-performance multiprocessor system with a reconfigurable interconnect, there is a need to compute a interconnect topology that will allow for a high-throughput load distribution on top of the physical processor array. In this paper, we investigate the problem of topology reconfiguration for Network on Chip (NoC) based multiprocessor arrays with faulty processing...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
Mismatched lattice constants between SiGe and silicon can cause the strain making the mobility improved. SiGe are grown underneath the channel apparently to form global strain over the whole devices, while Source/Drain refilled with SiGe would squeeze or pull up the devices uni-axially. The ID-VG characteristics curves and the maximum trans-conductance (gm) using strain engineering are observed to...
Strained Engineering including both global and local strains effectively enhances the mobility of carriers, in which global strains are generated by the mismatching of lattice constants at the junction of Si and Si0.775Ge0.225 and local strains are aroused by Source/Drain refilled with SiGe. In this paper, junction breakdown voltage, punch-through voltage, and the variation of threshold voltages are...
We report an ultrafast surface inspection method using a hybrid dispersion laser scanner. Using the technique, we demonstrate real-time detection of microparticles on silicon wafer surfaces at 1,000 times higher scan rates than conventional methods.
In this paper, two SOG structure micro heat pipes array (MHPs) with different length were fabricated, filled and tested. The MHPs were fabricated employing a silicon anisotropic etch technique. A new fill technology was used to inject the working fluid. The experiments were carried out to compare the effects of fluid fill rates between two MHPs with different length. The results revealed that for...
In this paper, we proposed a novel sensing scheme so-called Transmitter-Receiver Cooperative Sensing in a MIMO cognitive network by combining sensing information of both sides. Compared with most of the existing sensing schemes which simply use listen-before talk (LBT) only at the transmitter side, the proposed scheme can further improve the system performance by jointly feedback the Channel State...
It is widely recognized that process variations will have profound impact on nearly all aspects of future IC design. Depending on their sources, they are often categorized into two types: intrinsic variations and process-induced variations [1][2]. Process-induced variations are caused by the imperfection in silicon fabrication, varying from foundries to foundries. On the other side, intrinsic variations,...
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