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In this paper, a low-power Hamming distance associative processor employing time-domain techniques has been developed focusing on the implementation of an r-th nearest-match location identification function. The architecture not only inherits advantages of analog implementations on power consumption but also improves the accuracy of such implementations. This is because it employs digital technique...
A high-frame-rate dense motion vector field generation processor employing an efficient data manipulation scheme has been developed. The computation result of detecting a motion vector (MV) at each pixel location is reused in the adjacent location. As a result, the size of a best-match searching circuitry for MV detection has been reduced to 1/10 of that without data reuse. This allows us to implement...
A block-matching-based CMOS optical flow sensor architecture has been developed for real-time processing of moving images. In this architecture, an array of SIMD (single instruction multiple data) units calculate SAD (sum of absolute difference) values using only data from nearest-neighbor-units. As a result, it has become possible to carry out the block matching algorithm very efficiently with a...
A feature-vector-generation VLSI architecture has been developed aiming at building real-time image recognition systems based on the directional edge based algorithm. The functional cache memory developed in the present work cyclically buffers newly extracted edge flags from an input image, while supplying edge flags to a vector generation circuitry. As a result, it has become possible to generate...
An image feature extraction VLSI architecture using resonance current-voltage (I-V) characteristics has been proposed aiming at demonstrating a new potentiality of nano functional devices for use in building human-like intelligent systems. In this work, the resonance characteristics of nano devices have been emulated by CMOS inverter-based convolution circuits and directional edge filtering was carried...
A methodology for building a low-power high-capacity associative processor system employing nano functional devices has been proposed. The study is a demonstration of how to use nano-scale devices in building practical applications, particularly in building associative processors. Characteristics of such devices are utilized for similarity evaluation and emulated by a simple NMOS circuitry. The concept...
A methodology for building a low-power high-capacity associative system has been developed. In the system, matching cells having bell-shaped I-V characteristics play the role of similarity-evaluation elements and can be replaced by nanoscale quantum-effect devices. The study is aiming to extend the current CMOS designs to the coming era of nano-devices. A multi-core/multi-chip architecture has been...
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