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The globalization of the semiconductor industry has caused many challenges to prevent intellectual property (IP) piracy. Logic encryption is an effective technique for hardware IP protection. Researchers have proposed various logic encryption techniques, which introduce large overheads in delay, power and area. This paper aims to significantly reduce these overheads by proposing a novel gate replacement-based...
Packet-switched Network-on-Chip (NoC) is the shared global communication infrastructure for future large-scale chip multi-processors (CMPs). Recently, Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) on repeater-inserted wires to reduce packet delay was proposed. But current NoC with SMART support adds complexity to conventional routers and incurs high power consumption. In this paper,...
An indented antenna array is proposed for its low return loss and mutual coupling which may help to reduce the feedback in two-way full-duplex repeater. The essential idea is to take advantage of the different phase delays between the transmitting return and receiving paths created by the indention. An indention with linear progressive phase delays can make transmitting returns destructively combined...
Integrated circuits suffer from severe variation effects with technology scaling, making their timing behavior increasingly unpre-dictable. Timing speculation is a promising technique to tackle this problem with the help of online timing error detection and correction mechanisms. In this paper, we propose to use redundancy addition and removal (RAR) technique to optimize timing-speculated circuits...
With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guard band is not reserved. This work presents a novel insitu timing error masking technique, namely InTimeFix,...
By allowing the occurrence of infrequent timing errors and correcting them online, circuit-level timing speculation is one of the most promising variation-tolerant design techniques. How to effectively test timing-speculative circuits, however, has not been addressed in the literature. This is a challenging problem because conventional scan techniques cannot provide sufficient controllability and...
Region-based multi-supply voltage (MSV) design, by which circuits are partitioned into multiple “voltage islands” and each island operates at a supply voltage that meets its own performance requirement, is an effective technique to tradeoff power and performance. Different from conventional voltage island generation techniques that work in a conservative manner to guarantee “always correct” computation,...
As semiconductor manufacturing continues towards reduced feature sizes, yield loss due to process variation becomes increasingly important. To address this issue on FPGA platforms, several variation aware design (VAD) methodologies have been proposed. In this work we present a practical method of process variation characterization (PVC) to facilitate VAD using only intrinsic FPGA resources. The scheme...
The adaptive sliding mode control for a class of time varying delay systems with mismatched uncertainties and matched external perturbations are investigated in this paper. Based on the Lyapunov theory, a sufficient condition derived in terms of LMI is given to guarantee the existence of the sliding surface. The adaptive control is used to overcome the unknown upper bound of perturbations. Furthermore,...
Chain boiler combusting system is often seen and difficultly controlled in industry due to large delay time, varying coal's quality and steam load. In this paper a neural network identification method for time delay system and the parameter of delay time is discussed. We can acquire the best control value in term of the errors between predictive output and reference input, adjusting the parameters...
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