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Recurrent Neural Networks (RNNs) have the ability to retain memory and learn from data sequences, which are fundamental for real-time applications. RNN computations offer limited data reuse, which leads to high data traffic. This translates into high off-chip memory bandwidth or large internal storage requirement to achieve high performance. Exploiting parallelism in RNN computations are bounded by...
Deep learning is becoming increasingly popular for a wide variety of applications including object detection, classification, semantic segmentation and natural language processing. Convolutional neural networks (CNNs) are a type of deep neural network that achieve high accuracy for these tasks. CNNs are hierarchical mathematical models comprising billions of operations to produce an output. The high...
In this paper, the electric vehicle charging and discharging behaviours from the demand side is discussed. A large-scale charging of electric vehicles could jeopardize the safety and economics of the power grid operation. It is hence necessary to investigate the charging/discharging pattern involved in EVs and knowledge-based modelling technique is used to model their behvaiour. An improved particle...
There is a strong demand for both calibrating and testing the ADC performance before and after packaging for mixed-signal SoCs and SiPs. In this paper, we propose a built-in self-calibration scheme that offers digitally-controlled calibration of a pipelined ADC without using external stimulus. We further propose a self-testing strategy that uses the effective number of bits (ENOB) derived directly...
We propose a testing methodology for analog and radio-frequency (RF) circuitry that incorporates digital circuits for performance calibration and adaptation. We explore the reuse of built-in digital calibration circuitry, along with minor digital design-for-testability (DfT) modifications, to test and characterize analog/RF circuit performance. By observing the digital tuning signals captured in the...
The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration...
A fully integrated transmitter front end with on-chip power amplifier (PA) in 0.18 um CMOS technology is presented. The on-chip PA employs dynamic bias technique to reduce power consumption and enhance linearity. In the measurement, it reveals the output PldB of the PA is 26.5 dBm. Also, the transmitter delivers an average power of 17.3 dBm with EVM of -28.1 while drawing 225 mA of DC current (PA...
System level design is becoming the major design methodology for system-on-a-chip (SOC) design with IP (intellectual property) reuse to solve the productivity gap problem. How to synthesis efficient hardware from high level specifications, such as Java, SystemC or C++, is becoming an important issue. This paper presents a novel methodology to extract pipeline stages from high level behavioral models...
With the increasing demand of memories in system-on-chip (SOC) designs, developing efficient yield-improvement techniques for memories becomes an important issue. Built-in self-repair (BISR) technique has become a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA) function is usually needed for designing a BISR scheme....
Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-on-chips (SOCs). To increase the utilization of memory redundancy, the BISR technique usually needs to perform built-in redundancy-analysis (BIRA) algorithm for redundancy allocation. This paper presents an efficient BIRA scheme for embedded memory repair. The BIRA scheme executes the 2D redundancy...
Multi-format CD/DVD SoC, integrating an RF/AFE and a 1.5 Gb/s SATA PHY, is presented. It supports a 471Mb/s 18times DVD. A partial parity mode reduces SDRAM bandwidth and a power control mode minimizes the system clock rate. The 0.18mum CMOS SoC has 10M transistors, occupies 5.4 times 5.1mm2, and consumes 772mW during a 16times DVD read
We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a "macro command", to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety of heterogeneous memory modules in SOC, and it is not possible to test all of them with a single...
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