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A dual-gate ion-sensitive field-effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented. Non-ideal effects of the conventional ISFET, such as time drift and hysteresis, are suppressed by the innovative scheme in DGFET using the bottom poly-gate (PG)...
22nm node Si SOI Coplanar “N Channel Vertical Dual Carrier Field Effect Transistors” (VDCFET) and its SOC with effective channel length less than 10nm for communication applications are presented.
The critical issues in charge-based touch screen panels for large size display are noise and speed. To solve these, this paper introduces a two-point relative sensing based `Delta-Integration' scheme. It eliminates local noise and increases a readout difference between the touched and non-touched area. As a result, it can replace a high-resolution ADC with a comparator and counter. In addition, the...
The two steps RTP program for 32 nm NiPt silicide formation process has been evaluated to improve source-drain resistance (Rsd), resistance uniformity and device leakage reduction behavior. A lower RTP-1 process has been investigated over the Nickel rich silicide phase formation and physical defect reduction. A higher millisecond anneal (MSA) RTP-2 has been investigated of its process window on Nickel...
This paper presents the fabrication process and results of the 3D silicon carbide surface micromachined accelerometer compatible with CMOS processing. PECVD silicon carbide as mechanical material and aluminium as electrodes were used. Due to thermal budget of maximum processing temperature of 400degC, the sensor is fabricated on top of the CMOS readout circuit as a post-processing module. The sensor...
Low-power implementation techniques are used in the multimedia processor to achieve MPEG audio decoding in 6.33mW with a 1.1V supply. Three techniques are employed: a parallel processing DSP; dynamic voltage control using a multi-power domain; and a conditional pre-charge flip-flop. The processor occupies 6.5times6.5mm2 in 0.15mum 6M CMOS
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and...
Bulk CMOS transistors with NiSi fully silicided gate electrodes (FUSI) on plasma nitrided oxide gate dielectric are fabricated by a novel integration method using CoSi2 as Ni barrier layer on active regions. Performance improvements of 15% (NMOS) and 31% (PMOS) are demonstrated over poly gate electrode transistors at 35 nm gate length. FUSI impact on gate leakage, inversion oxide thickness, VT variation,...
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