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We have proposed a power supply circuit and an electrical interconnect test method based on charge volume supplied from the power supply circuit. We optimize the supply circuit so as for small resistive open defects that occur at interconnects among dies in 3D stacked ICs to be detected by the test method. We examine what resistive open defects can be detected with the optimized power supply circuit...
A power supply circuit and an electrical interconnect test method are proposed to detect open defects at interconnects between dies in 3D ICs. The test method is based on the amount of charge injected from the power supply voltage source. It is shown by Spice simulation that resistive open defects whose resistance is greater than 20Ω can be detected with the power supply circuit by the test method.
Resistive open defects in 3D ICs may change into hard open ones. In this paper, a built-in test circuit is proposed to monitor the changing process of the resistive open defects occurring at interconnects between dies embedding an IEEE 1149.1 test circuit. Feasibility of the process monitoring is examined experimentally in a PCB circuit made of ICs embedding the test circuit. It is shown that the...
A three-dimensional integrated circuit is fabricated by stacking multiple dies. A resistive open defect may occur at interconnects between the dies by a void and a crack during fabrication process. We have proposed an electrical test method for an IC made of dies in which boundary scan flip flops are not embedded. In this paper, testability of the test method for resistive open defects is examined...
In this paper, an electrical test method and a power supply circuit are proposed for open defects at interconnects between dies in a 3D IC. The test method is based on volume of charge injected from the power supply circuit. Feasibility of the electrical tests is examined by Spice simulation. The simulation results show that a hard open defect, capacitive ones and resistive ones whose resistance is...
A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation. It is shown by the...
An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value...
An electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. There is no need to add a circuit for the test method to an original circuit. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC...
A built-in sensor is proposed for detecting open faults in a 3D IC by means of appearance time of dynamic supply current. It is shown by Spice simulation that they can be detected with the sensor.
An estimation method of quiescent output voltage of a defective TSV is proposed at which a hard open defect occurs in a 3D IC. The method enables us to reduce the number of times of 3D electromagnetic simulation.
A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation and some experiments...
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