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The interconnection networks used by current fine grain FPGAs are not scalable for very big array sizes. To address this issue, we apply the GALS (globally asynchronous and locally synchronous) paradigm to build scalable FPGAs. The logic resources are divided into locally synchronous tiles and asynchronous communications among different tiles. To route the asynchronous communications, we build a serial...
The poor scalability of current mesh-based FPGA interconnection networks is impeding our attempts to build next-generation FPGA of larger logic capacity. A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed. In this paper, we propose sFPGA, a scalable FPGA architecture, which is a hybrid...
Current FPGA interconnect networks do not scale well, and use the major part of FPGA area. This has become a bottleneck towards the next-generation FPGAs of even larger logic capacity. To relieve this problem, the idea of using FPGA interconnects in a time-multiplexed way has been previously proposed. But to the best of authors' knowledge, no realization of such an architecture and its design flow...
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