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This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P2IP. The P2IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurability of the P2IP enables it to perform a wide range of image pre-processing tasks directly on a pixel...
Modern computing systems for vision have to support advanced image applications. They involve several heterogeneous pixel streams and they have to respect hard timing and area constraints. To face those challenges, an adaptable ring-based interconnection network-on-chip (NoC) has been recently proposed. This NoC is based on a new router architecture, with a dynamically adaptable internal datapath,...
This paper describes an original stream implementation of serially composed morphological filters using approximated flat polygons. It strictly respects a sequential data access. Results are obtained with minimal latency while operating within minimal memory space; even for very large neighborhoods. This is interesting for serially composed advanced filters, such as Alternating Sequential Filters...
The paper proposes a new parallel hardware architecture for a connected component tree computation. It is an original implementation of the recently published parallel algorithm based on building of a 1D tree for each individual image line and their progressive merging. The image is divided into independent partitions which are processed concurrently. Nevertheless, merging of these partitions requires...
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