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In many CMOS analog/RF circuits, such as passive mixers or N-path filters, the transistor operates as a switch. Switching circuits often experience source-drain reversal, and most transistor models exhibit discontinuities in second and higher-order derivatives of the drain current around zero drain-source bias. This introduces fundamental challenges in performing third-order inter-modulation distortion...
This demonstration presents a practical real-time full-duplex wireless link consisting of two full-duplex transceivers. Our prototyped full-duplex transceiver contains a custom-designed RF self-interference canceller and a National Instruments (NI) Universal Software Radio Peripheral (USRP). The discrete-component-based RF self-interference canceller emulates a compact RFIC implementation, which uses...
A fundamental challenge of full-duplex (FD) wireless [1] is the implementation of low-cost, small-form-factor, integrated shared-antenna (ANT) interfaces with low loss, low noise, high TX-RX isolation, and large TX power handling. Providing more TX-RX isolation in the ANT interface that is robust to environmental variations lowers the self-interference cancellation (SIC) and dynamic range required...
A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption...
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