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For precise system ESD simulation the transient chip behavior needs to be modeled accurately. As there are several typical characteristics possible (e.g. diode breakdown, snapback-element or forward diode) a straight forward methodology to build a generic model for transient behavior with destruction limits in SPICE is presented. This enables full-system transient ESD and electrical stress simulation...
Modeling of a 1-terminal ESD test setup is described. During the device stress a fast current pulse is forced only through a single pin of a semiconductor device. The model can be used to calculate voltage and current waveforms during the charging and discharging phase of an ESD event which takes place within a few nanoseconds. Charging and discharging of a device depends on the design and dimensions...
The introduction of the CDM Joint Standard has an impact on the electrical properties of the tester hardware due to updated waveform requirements. Models of different CDM discharge heads are generated using measurement data in frequency domain. Discharge currents of a device are simulated according to the different standards in time domain. In comparison to the popular but replaced JEDEC standard...
In this paper, approaches for the modeling and simulation of thermal destruction of ICs due to ESD are discussed from a system point of view. Considered systems consist of ESD generator, PCB, protection element, and IC. A direct connection between the ESD generator and the system is always assumed. For the modeling of an IC ESD destruction, the electric behavior model of an IC pin to ground or supply...
Charged Device Model (CDM) like stress represents the highest ESD risk during handling of single devices. Today air discharge compromises repeatability of CDM tests of products in a package. The paper demonstrates that the repeatable Capacitive Coupled TLP (CC-TLP) reproduces CDM failure signatures at both package and wafer level. Data will be shown to compare the stress failing level and the failure...
Accurate and flexible modeling of field coupling from ESD sources to cables or PCB traces (indirect ESD) is important for immunity estimations. Accurate circuit models can be obtained by applying approximations techniques to measurement data in frequency domain. In this paper an accurate ESD generator model is extended to model ESD coupling behavior for the ESD generator to a cable setup. The new...
Models of ESD generators according to IEC 61000-4-2 are required for failure simulations in order to predict e.g. the robustness of ICs or the performance of overvoltage protection elements. Due to significant variations between different generator types a flexible and fast method for individual characterization is needed. A new method is proposed here based on impedance measurements at the discharge...
The setup and the pulse generator for automotive component ESD testing are defined in the standard ISO 10605. Usually the DUT is placed directly on a horizontal coupling plane (HCP) or on a dissipative mat and the ESD generator is discharged via the DUT pins applying different charging voltages. The variance of test results in automotive ESD testing is high and one can not be sure if the components...
ESD events can cause numerous destruction effects in automotive electronic circuits. A prediction of ESD stress on system level is difficult and numerous iteration loops in the development process are necessary to fulfill the demands of automotive customers. A concept for system level ESD simulation is presented to predict robustness against ESD. Independent models of the different system components...
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