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This paper introduces a multi-loop fast transient response flipped voltage follower (FVF) low-dropout (LDO) voltage regulator suitable for system-on-chip (SOC) applications. While typical FVF-based LDOs exhibit fast transient response, which is critical for SOC applications, their output DC accuracy is limited due to low loop gain of the FVF. In this work, we introduce a multi-loop design aimed at...
This work presents the design of a high-bandwidth and high slew rate class-AB amplifier in a linear assisted hybrid converter for envelope tracking (ET) applications. ET has become prevalent for improving the efficiency of RF power amplifiers (PA) in portable devices when transmitting LTE signals. The class-AB amplifier in the hybrid converter provides the AC power to the PA, whereas the DC power...
A hybrid voltage-mode hysteretic boost converter is introduced in this work. The implemented control topology is practically self-stabilized due to the introduction of a current-limiting loop. A full range inductor current sensor and a hysteretic comparator are used to realize the current-limiting loop. A zero current detector is also implemented to enable a seamless transition from continuous to...
In Miller and current buffer compensation techniques, the compensation capacitor often loads the output node. If a voltage buffer is used in feedback, the compensation capacitor obviates the loading on the output node. In this paper, we introduce an implementation of a voltage buffer compensation using a Flipped Voltage Follower (FVF) for stabilizing a two-stage CMOS op-amp. The op-amps are implemented...
A new technique to decrease the transient recovery time in a very low-quiescent current low-dropout (LDO) voltage regulator is introduced. The new Transient Recovery Time Enhancement (TRTE) block comprises a voltage-to-current converter, current comparator and an NMOS output transistor. The proposed LDO using the TRTE block was fabricated in a 0.5-µm 2P3M CMOS process. The circuit operates at a total...
We report on a scheme to eliminate false codes generated due to switching delays among the output bits of an asynchronous parallel successive approximation analog-to-digital converter (SA-ADC) developed by Lin and Liu [1]. False output codes are eliminated by converting the binary outputs to Gray codes. A novel asynchronous parallel gray-to-binary converter is introduced to effectively reduce switching...
A new compensation technique known as tail compensation is applied to a two-stage CMOS operational amplifier. The compensation is established by a capacitor connected between the output node and the source node of the differential amplifier. For the selected opamp topology, tail compensation allows better performance in terms of bandwidth and power supply rejection ratio (PSRR) when compared to Miller...
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