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The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration...
During IO qualification's LUP tests in CMOS28nm Bulk technology, undesired ESD structure triggering has been found to be the root cause of LUP fails. Deeper test analysis identifies the combination of IOs abutment sequence that generate the fail. The understanding of the phenomenon is investigated through a specific TCAD simulation set-up.
This work presents an EOS characterization methodology for ESD clamps. BigFET-based and SCR-based power clamps with and without disable feature are characterized. Thanks to the proposed characterization methodology, robustness comparison is provided for the different ESD clamps, giving insights on improving IC robustness against undesired triggering during EOS events.
A product utilizing 5V RC clamps suffered EOS damage during BI due to marginal Vhold of the clamp NMOS. Powered TLP was used to mimic BI noise events and to explain clamp response across a range of starting Vsupply levels. Alternate clamp configurations were explored to improve Vhold.
This paper presents a novel self-protected IO concept based on a compact 3 ports ESD protection device [1]. Advantages compared to other ESD protection networks are demonstrated: compactness, flexibility and lower leakage. ESD demonstrators are processed in advanced CMOS to validate this concept, description and ESD results are presented.
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