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In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a...
In this paper, we propose efficient scalable nonvolatile flip-flops (NV-FF) with single-stage pulsed latch which is explored as the flip-flop core in hybrid CMOS/MTJ (magnetic tunnel junction) integration. Typical full-custom FF cores are implemented with a 28nm ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. The performance analysis takes into account...
In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and...
Paper presents a technology-independent metric for evaluation of logical masking properties of logic circuits and method for accurate reliability comparison of fault-tolerant logic designs. Proposed metric is based on the observability computation, providing certain trade-off between computational complexity and accuracy, reducing exponential complexity with regard to the number of elements to the...
In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB biasing scheme, simulations show that around 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes...
Many of the nanometer CMOS challenges are seriously compromising the gains attained with technology scaling, mainly impacting the yield and the circuit reliability. To cope with these problems, new design methodologies are necessary to improve the robustness of the circuits. Given the overheads associated with the traditional fault-tolerant approaches, alternative solutions, based on partial fault...
With technology downscaling, the vulnerability of combinational logic circuits to transient faults has increased resulting in error rates approaching those of memories. Thus, to guarantee a good use of selective hardening techniques, fast and accurate approaches for transient fault analysis in logic circuits are needed. In this work, we describe a methodology for Soft Error Rate (SER) evaluation in...
This paper investigates the design architecture and the optimum resistance state values for high-endurance, high-yield energy-efficient OxRAM-based non-volatile flip-flops (NVFF) for ultra-low power applications in 28nm FD-SOI. Silicon measurements demonstrate that a low programming current improves endurance, but at the expense of a reduced memory window (ROFF/RON). Statistical analyses show that...
Device-to-device communications are one of the most important challenges for cellular mobile communications. Professional Mobile Radio (PMR) networks could change the current standard for a new one based on 4G, when this type of communications will be included. PMR users such as police, fire brigades also use the D2D communications in under coverage and out of coverage scenarios. This type of users...
As professional mobile radio (PMR) networks evolve to a new generation based on Long Term Evolution (LTE), a new direct communication mode needs to be developed. Not only in PMR networks, but the increase of proximity services due to the explosion of the internet of things bring us to a new communication paradigm. The PMR users have very specific requirements and one of those is the ability to communicate...
We present in this paper the application of fault injection to selective hardening by triplication of a pipelined SPARC-V8 microprocessor. Fault injection is applied to identify the most sensitive flip-flops to single-event-upset and stuck-at faults of the design. The most sensitive flip-flops are replaced by triplicated ones during the physical implementation of the design. Selective triplication...
As wireless communications evolve towards heterogeneous networks, mobile terminals have been enabled to handover seamlessly from one network to another. At the same time, the continuous increase in the terminal power consumption has resulted in an ever-decreasing battery lifetime. To that end, the network selection is expected to play a key role on how to minimize the energy consumption, and thus...
As the wireless industry evolves towards heterogeneous networks, mobile terminals have been given the ability to handover from one network to another. The network selection process starts by a network discovery operation which involves scanning the candidate networks in order to collect the required information for handover decision. Such operation consumes a considerable amount of energy at the terminal-end...
Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This...
As CMOS technology enters the nanometer regime, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we compare different hardened architectures of the multiplexer...
As the dimensions of CMOS devices scale down to the nanometers, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we propose a defect-tolerant multiplexer architecture...
The rapid dimension scaling of CMOS has introduced many new challenges. One of them is to design reliable circuits with unreliable devices. Probabilistic transfer matrix (PTM) has proven to be an accurate method to evaluate the reliability of a combinational circuit. However, it requires a lot of time consumption and memory usage, which makes it unsuitable for large circuits. In this paper, we propose...
As technology scales down to the nanometer era, manufacturing defects are rapidly becoming a major concern in the design of electronic circuits. In this work, we present a defect-tolerant logic family constructed with CMOS cells. The basic idea of this approach is the construction of logic gates in which the outputs and their complementaries correct each other. We demonstrate, through circuit simulation...
As CMOS feature sizes are shrinking, manufacturing defects are becoming a growing concern in micro and nanoelectronics. This work deals with defect tolerance in FPGAs that are surely affected by technology downscaling. In this paper, we are interested in enhancing the defect tolerance of a switch box in a mesh of clusters FPGA, while trying to reduce the hardening cost. First, we had to spot, among...
In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input...
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