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The growing impact of the network on the overall power consumption of many-core systems introduces a need for mechanisms that reduce the power required for data communication without significantly impacting performance. This paper proposes a low-overhead mechanism for frequency control of individual channels in a Network-on-Chip system. The proposed mechanism is low-overhead, distributed and easy...
This paper presents an approach for improving the overall performance of a general purpose application running as a task graph on a many-core neuromorphic supercomputer. Our task graph framework is based on graceful degradation and amelioration paradigms that strive to achieve high reliability and performance by incorporating fault tolerance and task spawning features. The optimization is applied...
This paper presents an approach for generating fault tolerant task mappings of applications, represented as an application process graph (APG), to a many-core array. The approach uses a multi-objective evolutionary algorithm (EA) to evolve a range of viable task mappings through the optimization of fault tolerant properties and performance criteria. Fault tolerant properties are chosen to promote...
This paper presents XL-STaGe, a cross-layer tool for traffic-inclusive directed acyclic graph generation and implementation. In contrast to other graph-generation tools which focus on high-level DAG models, XL-STaGe consists of a set of processes that generate the task-graphs as well as a detailed process model for each node in each graph. The tool is highly customizable, with many parameters that...
Implementing Dynamic Voltage and Frequency Scaling (DVFS) is a non-trivial task on FPGAs and requires knowledge about the feasible voltage and frequency (VF) ranges as a first step. The VF feasible ranges depend not only on the size of the critical path in the design but also on the inter- and intra-die variability on the FPGA die. Moreover, the variations in the configuration of the FPGA highly affect...
Technology scaling is leading to extreme thermal challenges that make worst-case cooling system design unfavourable. On the other hand, on-chip communication, in terms of Network-on-Chip (NoC) workload, is expected to dominate Systems-on-Chip as a major heat source. In this paper a Runtime Thermal Management (RTM) design implementation for NoCs is proposed. Dynamic Programming Network (DPN) is introduced...
Network-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and has satisfied different demands in terms of high performance and economical interconnect implementation. However, merely metal based NoC pursuit offers limited scalability with the relentless technology scaling, especially in one-to-many (1-to-M) communication. To meet the scalability demand,...
This study proposes a new method for designing adaptive routing algorithms for three-dimensional (3D) networks-onchip (NoCs). This method is based on extending the existing 2D turn model adaptive routing to a 3D scenario. A 3D planebalanced approach with maximal degree of adaptiveness is achieved by applying a well-defined set of rules for different strata of the 3D NoC. The proposed method is applicable...
Adverse effects of unreliable on-chip power supply delivery are exacerbated due to the rapid shrinking of device dimensions and the ever increasing power consumptions in nanometre-scale integration. Power supply integrity becomes a critical concern. Particularly, on-chip communication networks, such as networks-on-chip (NoC), dictates power dissipations and overall system performance in multi-core...
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