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FPGA is a promising hardware accelerator in modern high-performance computing systems. In such a system, power is a key factor in the design requiring thermal and energy-saving considerations. Modern power estimators for FPGA either support specific hardware provided by FPGA vendors or contain power models for certain types of conventional FPGA architectures. However, with technology advancement,...
We propose embedding hard NoCs on FPGAs to improve system-level communication as detailed in our previous studies [1–6]. This demo paper outlines the three main design and simulation tools that we have been using to experiment with Embedded NoCs on FPGAs.
FPGA circuit design, and thus the unique computing power of FPGAs is currently mostly only accessible to experts working in the field. The Hastlayer project aims to give a tool to software developers familiar with the .NET platform to automatically transform performance-critical parts of their programs into seamlessly usable FPGA-implemented hardware, yielding faster program execution and lower power...
Cool Mega Array (CMA)-SOTB-2 is an ultra-low energy Coarse Grained Reconfigurable Architecture[1] (CGRA) for recent advanced sensor networks, Internet of Things and wearable computing. It has a large Processing Element (PE) array without memory elements for mapping an application's data-flow graph, a small simple programmable μ-controller for data management, and data memory. Unlike traditional coarse...
Energy efficiency is one of the major challenges in datacenters, and a promising way to tackle it are microservers. These scaled down machines with smaller CPUs, less peripherals and tighter integration improve energy efficiency, but often at the expense of lower performance. In this work we explore the tailoring of standard software components to specialized hardware as a way to get the energy efficiency...
Wide portfolio of new technologies in design and manufacturing of advanced integrated circuits enabled higher integration of complex structures at ultra-high nanoscale densities, however they are subjects to sensitivity to various changes of the internal nanostructures and their parameters, resulting in the requirement of advanced measurements and complex reliability assessments. This contribution...
The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the budget of the wider community. In order to make and validate timely and relevant new contributions, the wider community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks. We demonstrate...
All-digital radios allow the full digitalization of the radio system which poses an important step towards the complete software description of RF signals proposed in SDR. Using digital signal processing techniques and the integration of the radio into a single digital chip, it is expected that high flexibility in these systems will be fundamental for the next generation of wireless networks. In addition,...
Hardware task scheduling and allocation at runtime increase the chip utilization ration and improve the system performance by exploring partially reconfigurable Field-Programmable Gate Arrays (FPGAs). Partial reconfiguration enables to change all or parts of the system hardware during the execution, in order to gain efficiency over static system. Hardware-software real-time operating systems (RTOS)...
This paper presents the architecture and implementation of an FPGA-based all digital transmitter for wireless radio communications. These transmitters allow a greater degree of flexibility for the carrier frequency, signal bandwidth and the use of simultaneous multiple-standards. Latest advances in the state-of-the-art in this emerging area are presented as well as the remaining issues to be solved...
The ever-growing design complexity of modern embedded systems and the need for lower energy consumption have lead to design techniques which target to bridge the gap between the designer's productivity and the design complexity. In particular, Virtual Prototyping enables the system modeling and simulation in multiple abstraction levels, while the automated Design Space Exploration (DSE) targets to...
The presented Ph.D. work deals with the development of a framework to support the design of embedded systems. In particular, it focuses on the development of a unobtrusive profiling system to support, at run-time, both the definition of the best execution platform and its resource optimization. The final goal is the definition of a framework exploiting reconfigurable logic, based on monitoring actions...
Accelerator-coupled systems have been introduced as a promising architectural paradigm that can boost performance and improve power of general-purpose computing platforms. This research focuses on the accelerators' scalability problem due to resource under-utilization in FPGA-based accelerator-coupled platforms. By recognizing that static memory allocation the de-facto memory management mechanism...
In this work we present a concept of an architecture design flow for heterogeneous reconfigurable architectures. We have a special focus on high flexibility regarding the architecture design. We cover architectures from fine-grained island-style FPGAs and heterogeneous hierarchical structures through to coarse-grained reconfigurable architectures (CGRAs). Our goal is to make the development and optimization...
In this Ph.D. work it is intended to explore innovative agile and wideband FPGA-based Software Defined Radio (SDR) receiver architectures for future 5G wireless communications. This short paper presents some preliminary work in this area, including interesting results of an innovative SDR receiver. This new architecture implements the analog-to-digital conversion directly at RF stage based on Pulse...
Multi-Processor System-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection architectures determining various trade-offs between cost and performance. An automated methodology for optimizing FPGA-based MPSoC interconnect architectures is summarized in this poster paper. Based on the application communication requirements, the methodology concurrently defines the...
To eliminate the overhead of zero padding in sparse matrix-vector multiplication (SpMxV), prior works have been focusing on partitioning a sparse matrix into row vectors sets (RVS's) or sub-matrices. Nevertheless, performance degraded still due to the sparsity pattern of a sparse matrix. In this paper, we propose a heuristics, called recursive merging, which uses greedy approach to recursively merge...
The first International Conference on Field-Programmable Logic and Applications (FPL) was held in 1991 at Oxford University. In the ensuing years, it has grown to become the largest conference covering the rapidly growing area of field-programmable logic. Many of the advances achieved in reconfigurable system architectures, applications, embedded processors, design automation methods and tools were...
The list of significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented in this paper. These 27 papers represent those which have most strongly influenced theory and practice in the field.
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