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In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
In this paper, the effects of nanowire (NW) line-edge roughness (LER) in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) are investigated by 3-D statistical simulation in terms of both performance variation and mean value degradation. A physical model is developed for NW LER induced performance degradation in SNWTs for the first time. The results indicate large performance mean value degradations...
The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths. Especially, the LER of nanowires, which contains two...
The design of silicon nanowire MOSFETs (SNWTs) for RF applications is discussed in this paper based on 3-D simulation, including the impacts of the parasitic capacitances and resistance. The results indicate that large parasitic capacitances are a dominant factor for nanowire structure, which can significantly degrade the ac characteristics of SNWTs. Resistance of the ultranarrow source/drain extension...
- In this paper, the analog/RF performance and reliability behavior of silicon nanowire transistors (SNWTs) are investigated. Analog/RF Figures-of-Merit (FoMs) of SNWTs are studied, including transconductance efficiency, intrinsic gain, cutoff frequency and maximum oscillation frequency. The impact of device parameter fluctuations is also evaluated. In addition, hot carrier injection (HCI) and negative...
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