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In this paper, a built-in supply current test circuit is proposed to detect open defects occurring at interconnects between dies including an IEEE 1149.1 test circuit and locate the defective interconnects in a 3D IC. Feasibility of interconnect tests with the test circuit is examined by some experiments with a prototyping IC in which the test circuit is embedded and by Spice simulation. The simulation...
Fault scrambling technique is considered a promising way to distribute faulty bits into different code words such that the number of faulty cells in each codeword is below the protection capability of the adopted EDAC coding techniques. However, the effectiveness of the scrambling technique depends on the determination of the row/column scrambling control words. Therefore, we propose a heuristic algorithm...
An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value...
In this paper, we propose a test method for detecting pin opens of CMOS logic ICs in assembled PCBs. The test method is based on supply current of a circuit under test which flows when a time-varying signal is provided to a targeted pin with a test probe as a stimulus. Test signal's amplitude is less than VDD. Test vector generations are not needed for the tests. In the test, the test probe also can...
An electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. There is no need to add a circuit for the test method to an original circuit. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC...
In this paper, a built-in test circuit of electrical tests is proposed to detect pin opens of CMOS ICs. When a circuit is tested by the test method, current is made to flow through a targeted pin. An open defect is detected by means of the difference between the current of a defect-free circuit and the measured one. Feasibility of tests with the built-in supply current test circuit is examined by...
Three-dimensional integration is considered a promising solution to cure the challenges of performance, power consumption, quality, and reliability issues. The feature of 2.5D ICs is that the dies are stacked on a passive silicon interposer and the dies communicate with each other by means of TSV-based interconnects and re-Distribution layers (RDL) within the silicon interposer. This paper aims to...
In this paper, a Design-for-Testability method is proposed to detect an open defect occurring at an interconnect between dies in a 3D IC. The open defect is detected by means of a supply current flowing whenever a time-varying voltage signal is provided to the targeted interconnect as a test input stimulus. Feasibility of the test method is examined by targeted experiments and circuit simulations...
A built-in sensor is proposed for detecting open faults in a 3D IC by means of appearance time of dynamic supply current. It is shown by Spice simulation that they can be detected with the sensor.
An estimation method of quiescent output voltage of a defective TSV is proposed at which a hard open defect occurs in a 3D IC. The method enables us to reduce the number of times of 3D electromagnetic simulation.
A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation and some experiments...
Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant...
Instead of merely using redundant rows/columns to replace faulty cells, error-correcting codes are also considered an effective technique to cure permanent faults for the enhancement of fabrication yield and reliability of memories. However, if the number of faulty bits in a codeword is greater than 1, the protection capability of the widely used SEC-DED (single-error correction and double-error detection)...
In this paper, a built-in electrical test circuit is proposed to detect an open defect at an interconnect between a land in a printed circuit board and an IC. An inverter gate is used as an open sensor in the test circuit. An AC voltage signal is provided to a targeted interconnect and the sensor as a test input signal to detect the defect. The defect is detected by means of supply current of the...
In this paper, a built-in test circuit is proposed to detect and locate open defects occurring at interconnects between dies in a 3D IC by means of the quiescent supply current. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. Testability of the testing with the test circuit is evaluated by Spice simulation. The simulation results show...
In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments...
In this paper, a built-in test circuit is proposed to detect open defects that occur at interconnects between dies inside 3D ICs. An inverter gate is used in the test circuit as an open sensor. Open defects are detected by means of supply current of the inverter gate flowing when an AC voltage signal is provided to targeted interconnects as a stimulus. The interconnect at which an open defect occurs...
This paper presents a design-for-testability method for detecting delay faults. In order to observe the effect of small delay defects, we present modified boundary scan cells in which a time-to-digital converter (TDC) is embedded. In our boundary scan cells, flip-flops are utilized for both making a scan path and capturing circuit response. The architecture of the boundary scan design is proposed...
In this paper, we propose a supply current testable resistor string DAC of decoder type whose area overhead is small and a supply current test method. Open defects and short ones in the DAC can be detected by the test method with about 50% of the exhausted test vectors. It is shown by some experiments that most of the targeted defects in our testable DACs of 4 and 8 bits can be detected by the test...
In this paper, a method for reducing test data volume of BIST-aided scan test (BAST) is proposed. In our BAST method, scan chains are ordered using compatible flip-flops to reduce the conflicting bits between ATPG pattern and random pattern obtained by LFSR. The inverter block in BIST-aided scan architecture is modified for shifting inverter code such that the random pattern produced by LFSR has less...
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