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Checkpoint recovery (CR) is a classic fault-tolerance technique, which enables computing systems to execute correctly even when affected by transient faults. Although a number of software and hardware based approaches for CR does exist, these approaches usually are either too large, too slow, or require extensive modifications to the software and the caching/memory schemes. In this paper, we propose...
Checkpoint/recovery, as a classic method, has been widely used for overcoming transient faults in computing systems. The basic function of checkpoint/recovery is to save the system states periodically and to restore the system states by using the saved states if a fault occurs. With the hardware-implemented checkpointing mechanism executing at runtime, a processor will have substantially increased...
This paper presents a novel approach to improve the existing Binary-to-RNS multi-moduli architectures (MMAs). These MMAs reduce the complexity by sharing common intermediate circuitry among various RNS moduli channels. Two types of MMAs are distinguished depending on whether the functionality is implemented in serial or parallel. An existing input pre-computation methodology, which improves the performance...
Pipeline of processors allow the execution of a sequential streaming program on multiple processors. However, partitioning sequential code for Multiprocessor Systems-on-Chips (MPSoCs), and then creating the MPSoC platform for the sequential code to execute, is a challenging problem. Parallelizing/pipelining statements within a control loop will improve the throughput of each iteration and the overall...
Power based side-channel attacks attempt to obtain the secret key from implementations of cryptographic algorithms, such as Advanced Encryption Standard (AES), by analyzing the power traces during execution. Such attacks employ statistical methods to find correlations of power traces with parts of the secret key. In order to be effective, a countermeasure must remove or conceal such a signature. Previous...
The need for Multiprocessor Systems-on-Chip (MPSoCs) to satisfy performance demands of applications in embedded systems has enabled vendors to create different communication architectures for MPSoCs. It is a challenge to rapidly identify the best communication architecture and its best configuration, in terms of task mapping and buffer size, for a given application. In this paper, we propose a novel...
The ubiquity of wireless devices has created security concerns on the information being transferred. It is critical to protect the secret information in every layer of wireless communication to thwart any type of attacks. A dynamic reconfigurable puncturing based security mechanism, named RePunc, is proposed in this paper to provide an extra level of security at the physical layer. RePunc utilizes...
Security of embedded computing systems is becoming paramount as these devices become more ubiquitous, contain personal information and are increasingly used for financial transactions. Side Channel Attacks, in particular, have been effective in obtaining secret keys which protect information. In this paper we selectively classify the side channel attacks, and selectively demonstrate a few attacks...
Future on-chip manycore systems are expected to have hundreds of cores, and to be used for a number of applications to amortize their fabrication costs. In this paper, we examine how software pipelines, which are useful for streaming/multimedia applications, can be efficiently executed on a manycore system with shared memory. The goal is to balance the stages of the pipeline under workload and resource...
Multicore systems are an integral part of today's embedded systems which allow for improved performance and reduced power consumption. Designing and creating a multicore system is challenging. Verification and validation of the designed multicore system incur significant cost and effort. A simpler design process will allow even the software engineers to design multicore systems and evaluate their...
Wireless communication is an indispensable tool in our daily life. Due to the open nature of wireless channels, wireless communication is more vulnerable to attacks than wired communication. Security is paramount in wireless communication to overcome these attacks. A reconfigurable convolutional encoder/decoder based physical layer security mechanism, named ReConv, is proposed in this paper. ReConv...
Advanced Encryption Standard (AES) is arguably the most popular symmetric block cipher algorithm. The commonly used mode of operation in AES is the Electronic Codebook (ECB) mode. In the past, side channel attacks (including power analysis based attacks) have been shown to be effective in breaking the secret keys used with AES, while AES is operating in the ECB mode. AES defines a number of advanced...
Network on Chip (NoC) is a sophisticated communication infrastructure that provides quality of service (QoS) guarantees for a complex Systems-on-Chip (SoC) application. Some applications demand guaranteed end-to-end latency. Mapping algorithms are used to map an application on an NoC to satisfy the bandwidth constraints and end-to-end latency requirements. The design of the mapping algorithms determines...
Power analysis attacks are one of the most common Side-Channel Attacks (SCAs), proven to be extremely successful even on protected embedded devices. This paper proposes the use of a Residue Number System (RNS) architecture with randomly permuted moduli sets to implement the Double-and-Add computation, which is proven as the most susceptible operation in Elliptic Curve Cryptography (ECC). The proposed...
The Multiprocessor System-on-Chip (MPSoC) paradigm as a viable implementation platform for parallel processing has expanded to encompass embedded devices. The ability to execute code in parallel gives MPSoCs the potential to achieve high performance with low power consumption. In order for sequential legacy code to take advantage of the MPSoC design paradigm, it must first be partitioned into data...
It is widely known that Multiprocessor Systems-on-Chip (MPSoC) is the driving force behind many embedded devices. State-of-the-art mobile phones and gaming consoles contain more than four processors in their MPSoC. Performance counters have become the recent trend in these devices to perform runtime adaptations to match power and performance budgets. In this paper, we propose a scalable performance...
Soft error has become a major adverse effect in CMOS based electronic systems. Mitigating soft error requires enhancing the underlying system with error recovery functionality, which typically leads to considerable design cost overhead, in terms of performance, power and area. For embedded systems, where stringent design constraints apply, such cost must be properly bounded. In this paper, we propose...
Advanced Encryption Standard (AES) is one of the most widely used cryptographic algorithms in embedded systems, and is deployed in smart cards, mobile phones and wireless applications. Researchers have found various techniques to attack the encrypted data or the secret key using Side Channel information (execution time, power variations, electro migration, sound, etc.). Power analysis attack is most...
The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. The interleaving, one of the key components in the communication baseband, varies in differing communication protocols. A novel reconfigurable variable increment step (VIS)...
Mapping tasks to cores in an Multiprocessor System-on-Chip (MPSoC) to meet constraints is widely investigated. Thus far the data flow graphs used for binding have been limited to acyclic graphs or have been single rate. In this paper we generalize the approach by allowing DFGs to be cyclic and multi rate. We further improve energy consumption by setting frequency per core in a Globally Asynchronous...
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