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Networks-on-Chip (NoC) gradually becomes a main contributor of chip-level power consumption. Due to the temporal and spatial heterogeneity of on-chip traffic, existing power management approaches cannot adapt the NoC power consumption to its traffic intensity, and hence lead to a suboptimal power efficiency. They either resort to over-provisioned NoC design that only suits for traffic spatial distribution,...
There are four major components in application systems with internet-of-things (IoT): sensors, communications, computation and service, where large amount of data are acquired for ultra-big data analysis to discover the context information and knowledge behind signals. To support such large-scale data size and computation tasks, it is not feasible to employ centralized solutions on cloud servers....
Design of fully synchronous System on Chip is becoming a challenging task. This task is even more difficult in advanced nodes and 3D designs, where the local and global variability can turns the timing closure an overwhelming task. In this way, the use of asynchronous circuits for long link and 3D link communication can provide better robustness to both local and inter-die variability and achieve...
Low uniqueness and vulnerability to machine-learning attacks are known as two major problems of Arbiter-Based Physically Unclonable Function (APUF) implemented on FPGAs. In this paper, we implement Double APUF (DAPUF) that duplicates the original APUF in order to overcome the problems. From the experimental results on Xilinx Virtex-5, we show that the uniqueness of DAPUF becomes almost ideal, and...
This paper presents an oscillator-based true random number generator (TRNG) that automatically adjusts the duty cycle of a fast oscillator to 50 %, and generates unbiased random numbers tolerating process variation and dynamic temperature fluctuation. Measurement results with 65nm test chips show that the proposed TRNG adjusted the probability of ‘1’ to within 50 ± 0.07 % in five chips in the temperature...
We address the problem of formally verifying nonlinear analog circuits with an uncertain initial set by computing their reachable set. A reachable set contains the union of all possible system trajectories for a set of uncertain states and as such can be used to provably check whether undesired behavior is possible or not. Our method is based on local linearizations of the nonlinear circuit, which...
This paper proposes an area efficient device parameter estimation method with sensitivity-configurable ring oscillator (RO). This sensitivity-configurable RO has a number of configurations and the proposed method exploits this property for reducing sensor area and/or improving estimation accuracy. The proposed method selects multiple sets of sensitivity configurations, obtains multiple estimates and...
Thin-film, solid-state microbatteries represent now a viable alternative for powering small form-factor microsystems or storing the power harvested by energy microsensors. One major obstacle to their widespread use in integrated systems has been the absence of a high-fidelity, physics-based, compact model describing their operation and enabling their design and verification in the same CAD environment...
In this article, we propose a new parallel matrix solver, which is very amenable for Graphic Process Unit (GPU) based fine-grain massively-threaded parallel computing. The new method is based on the graph-based symbolic analysis technique to generate the computing sequence of determinants in terms of determinant decision diagrams (DDDs). DDD represents very simple data dependence and data parallelism,...
Machine learning algorithms are advocated for automated diagnosis of board-level functional failures due to the extreme complexity of the problem. Such reasoning-based solutions, however, remain ineffective at the early stage of the product cycle, simply because there are insufficient historical data for training the diagnostic system that has a large number of test syndromes. In this paper, we present...
CPU caches have become an essential component in many computer systems as they can significantly increase system performance by alleviating the effects of memory latency. For many designers part of the system design flow is the selection of an appropriately configured cache, a task which can be performed using cache simulators. Exploring the entire design space through precise cache simulation is...
Probing attack is a severe threat for the security of hardware cryptographic modules (HCMs). In this paper, we make the first step to evaluate the vulnerability of HCMs against probing attack, wherein we investigate the probing complexity and the key candidate reduction capability for probing attack on every signal in the circuit. We also present approximate solutions for the calculation of the proposed...
In japan, Telecommunications Authority supposed the first grand schedule for launching and spread of UHDTV & advanced smart TV, called ‘roadmap’, in June 2013. The roadmap suggested that business-based 4KTV & 8KTV broadcast would be launched until 2020. In 2014, experimental 4K broadcast started and ‘roadmap’ was revised. Comprehensively, grand schedule for launching UHDTV in Japan is said...
The 4K2K Display market is expanding faster than expected. For this market, we introduce the world's 1st Complete-4K SoC solution with hybrid memory system. This SoC supports High Efficiency Video Coding (HEVC) 10bit 4K 60p decode, graphics processing, picture blending, and external video input/output. These operations can be performed simultaneously with 4K quality. To realize that capability, we...
In recent years, the growing demand for ultra-high-definition television (UHDTV) services has generated the rapid development of UHDTV technologies. A key issue in providing UHDTV services is achieving efficient video coding. This paper presents an outline of H.265/HEVC, the latest video coding standard, and reviews the technologies it includes.
Electron beam lithography (EBL) is a very promising candidate for integrated circuit (IC) fabrication beyond the 10 nm technology node. To address its throughput issue, the Character Projection (CP) technique has been proposed, and its stencil planning can be optimized with aware of overlapping characters. However, the top level 2D stencil planning problem has been proved to be an NP-hard problem...
To handle complexity, embedded software is usually divided into components that are developed independently from each other and then need to be integrated in a reliable and deterministic manner. This involves buffering and synchronizing exchanged signals, as well as finding a feasible execution schedule, which is a tedious and error-prone procedure. We propose a model of computation that enables a...
A critical aspect in SoC design is the correctness of communication between system blocks. In this work, we present a novel approach to formally verify various aspects of communication models, including timing constraints and liveness. Our approach automatically extracts timing relations and constraints from the design and builds a Satisfiability Modulo Theories (SMT) model whose assertions are then...
The high performance demand of embedded systems along with restrictive thermal design power (TDP) constraint have lead to the emergence of the heterogenous multi-core architectures, where cores with the same instruction-set architecture but different power-performance characteristics provide new opportunities for energy-efficient computing. Heterogeneity introduces challenges in scheduling the tasks...
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