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Despite the exceptional progress of MPSoC architectures, on chip communication networks remain a lock for the evolution of their performances due to the power consumption and the delay in data carrying. In this context, the wired radio frequency (RF) network on chip (RFNoC) has emerged. In this paper, we developed a library of RF component models in VHDL-AMS for time domain simulation. This library...
The radio frequency network on chip (RFNoC) is proposed as a solution to the network on chip issue. The maximizing of the number of the communication paths is required to increase the aggregate throughput. According to the configuration of the RFNoC and the organization of the repartition of the available spectral resources, the quality of the signal may be influenced. An analysis of the effect of...
A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide...
This paper introduces flexible radio techniques inside integrated circuits in order to tackle the interconnect issue for many-core chips. We propose to take benefits from OFDMA for a RF-interconnect associated to a carrier allocation policy and adaptive modulation. A 20 GHz bandwidth is shared between 32 tile sets made of 32 tiles of 4 cores each, for a 4096 cores chip. We adopt a cognitive radio...
We propose in this paper a power adaptive zero-IF receiver based on a wide-band Low Noise Amplifier (LNA) dedicated to wireless home communications operating from 0.8GHz to 11GHz. Two different operation modes (low power consumption mode and high performance mode) controlled by bias conditions are applied to this LNA. The bit rate error (BER) estimated by the Q-factor of eye diagram is used as mean...
This paper describes a simple technique for on wafer passive multi-port circuits characterization. This method gives an efficient measurement of the scattering S-parameters of these devices at their ports reference planes. Furthermore, it provides cost saving in terms of used wafer surface and equipments by using an universal two-port Vector Network Analyzer (VNA). This method is applied to the characterization...
A design methodology of reconfigurable distributed low noise amplifier (RDLNA) dedicated for wireless home communications operating from 0.8GHz to 11GHz is presented in this paper. This RDLNA is suitable to operate in two different operation modes: low power consumption mode and high performance mode. The used technology is 0.15μm InGaAs Active Layer pHEMT Process provided by TRIQUINT. The circuit...
In this paper, we propose a new model of skin effect in time domain to perform mixed simulations using VHDL-AMS. It is used for RF interconnects but can be implemented in other applications. The skin effect is described by the resistances behavior as a function of square root of the frequency. We use the Laplace domain to have an access to the frequency in a time domain simulation, and to approximate...
In the context of future System on Chip (SoC) there is a need for efficient tools to explore the capabilities of future Network on Chip. In this paper we present a behavioral model of a RF-Interconnect system which can offer an alternative to classical global interconnects. The model was developed with VHDL-AMS. The simulation results are compared to electrical ones, and show good agreement. The new...
The noise parameters are usually measured by a multi-impedance method. We propose a new method which requires a lighter equipment using a numerical process. It consists in using an inverse Fourier's transform in order to identify the correlated from the non-correlated parts of the measured noise power.
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