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The SystemC AMS extensions that have been standardized by OSCI in March 2010 have triggered a number of research projects and activities. This invited session gives an overview of ongoing research based on and related to SystemC AMS extensions. The first three papers describe concrete modeling examples. The last paper proposes a new kind of solver that is able to simulate the ELN model of computation...
Computer-aided design has been traditionally applied to computers and embedded systems but not to the communication infrastructure among them. The paper contributes to fill this gap by proposing to use a mathematical language to model a distributed application in terms of tasks, hosting nodes, and interactions with the environment. Tasks are described in terms of computation and communication requirements...
SystemC is a widely used tool for prototyping Systems-on-a-Chip. Being implemented as a C++ library, a plain C++ compiler is sufficient to compile and simulate a SystemC program. However, a SystemC program needs to be processed by a dedicated tool in order to visualize, formally verify, debug and/or optimize the architecture. In this paper we focus on the tools (called front-ends) used in the initial...
On FPGA-platforms, the feature of dynamic partial reconfiguration offers a wide range of applications. We propose a new formal method for design, analysis, and verification of the reconfiguration process on such devices. The π-calculus, also known as the calculus of mobile processes, is a type of process algebra typically used to describe dynamic communicating processes. We propose the π-calculus...
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults. Approaches to implement fault tolerance are known e.g. on architecture level, algorithmic level, or layout level [1], [2]. But assessing the fault tolerance of a given circuit is a hard verification problem.
Formal specifications used in automatic verification typically describe the desired behavior of a system only in absence of environment failures. That is, specifications are often of the form A → G, where A is an assumption on the environment and G is the guarantee, the system should provide. This approach leaves the behavior of the system unspecified when A is not fulfilled and neither verification...
Reversible logic serves as a basis for emerging technologies like quantum computing and additionally has applications in low-power design. In particular, since traditional technologies like CMOS are going to reach their limits in the near future, reversible logic has been established as a promising alternative. Thus, in the last years this area started to become intensely studied by researchers. In...
Today's system-on-chip (SoC) systems must be designed as quickly as possible by integrating IP blocks from diverse suppliers. In this paper, we present a new automata-based algorithm that automatically synthesizes glue logic for SoC fabrication and Transaction-level modelling (TLM) transactors for SoC modelling. Our approach introduces a new encoding for state variables which captures data conservation...
Model Driven Architecture (MDA) and Electronic System Level (ESL) design are key approaches for succeeding in the specification and design of current embedded systems, which are increasingly complex and heterogeneous. MARTE is the most advanced UML profile for abstract specification of real-time embedded systems in the MDA context, while SystemC is the language most widely adopted by the ESL design...
Network-on-chip (NoC) has been accepted as a viable solution to cope with ever increasing communication demand in future many-core system-on-chips with hundreds to thousands of heterogeneous cores. Developing and manufacturing these complex NoCs are not feasible without early system validation by using high-level simulation. This paper proposes an architectural transaction level modelling technique...
In recent times, range based modeling and simulation techniques have emerged for systems with parameter tolerances and deviations. They are used to perform a semi-symbolic simulation and to analyze the examined systems for their time domain behavior. The system quantities in such simulations are represented as range based signals using the concept of Affine Arithmetic. Transforming the range based...
A typical CMOS photonic circuit may comprise analog, digital and optical devices. To simulate it, a common simulation environment for electrical/optical systems is necessary. In this article, a simulation methodology for CMOS photonic heterogeneous system has been proposed. Using hardware description language, we create behavioral models for optical devices with S-matrix formalism. The challenges...
A bottleneck during hardware design is the localization and the correction of faults — so-called debugging. Several approaches for automation of debugging have been proposed. This paper describes a methodology for evaluation and comparison of automated debugging algorithms. A fault model for faults occurring in SystemC descriptions at design time or during implementation is an essential part of this...
The concept of multiple class inheritance is a feature that many Object-Oriented Programming (OOP) languages have where a subclass can inherit behaviors (i.e. class methods and properties) from more than one superclass. As the language is currently defined, a SystemVerilog subclass (child class) can only extend from a single superclass (parent class). This paper presents some of the problems having...
Evaluating the sensitivity of digital integrated systems with respect to soft errors has become an important part of the design flow for many applications. This presentation quickly discusses the most typical approaches used today to analyze the robustness from the application viewpoint.
The first paper defines an operational model for specifying application specific programmable modules, and a methodology to perform the automatic generation of safety properties as well as the formal proof of correctness of a pipelined implementation. The second paper presents a typology of programming and design faults, and characterizes them as a mutation of the design Control Dependence Graph,...
In this paper a system level design approach is presented, which reduces the effort of integrating low level tools for the evaluation of different solutions during design space exploration. Thereby, low level estimation tools can be utilized for a fast and accurate estimation of the power consumption of different HW/SW architectures. The proposed design flow extends the known separation of communication...
For checking the temporal behaviour of embedded systems, real-time scheduling analysis based on abstract, formal models is a well-established method. A major difficulty for such analytical models in practical use-cases is the non-trivial representation of a real implementation model. To overcome this limitation we propose a formal mapping of a concurrent, object-oriented, executable implementation...
This paper suggests an operational instruction set architecture (OISA) model for specifying weakly programmable IPs (WPIPs). WPIPs are application-specific programmable System-on-Chip (SoC) modules such as application-specific instruction set processors (ASIPs). The individual instructions of WPIPs often implement large segments of an application algorithm corresponding to hundreds of conventional...
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