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This study presents an experimental analysis of the Xray radiation effect on the drain induced barrier lowering (OIBL) of strained and unstrained, p and n type triple gate SOI MuGFETs. In both types of devices, the narrow fin transistors are more immune to radiation because of the better coupling among the gates. It is shown that total dose damage in nMuGFETs always leads to a performance degradation,...
The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain...
A single transistor 1T-DRAM, also called Floating-Body RAM cell (FBRAM) makes use of the transistor floating body as a charge storage node. Nowadays, it has become of high interest because it overcomes the integration problems associated with the capacitor of the conventional 1T/1C DRAM. In order to improve the retention time and sense margin, the parasitic BJT (Gen2) programming shows the best performance...
The continuous reduction of the devices has driven the scientific community to explore alternative technologies that are compatible with CMOS technology, but with different operating principles. The Tunnel Field Effect Transistors (TFETs) are a new conception of devices that have been proposed as a promising option to replace conventional MOSFETs, since its physical structure allows a very steep subthreshold...
In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved...
The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed,...
The harmonic distortion (HD) exhibited by unstrained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin. The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of...
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