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Many authors have shown how to break the AES cryptographic algorithm with side channel attacks; specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present two practical timing attacks on NoC that improve Prime+Probe technique, the P+P Firecracker, and P+P Arrow. Our attacks target the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore,...
Many authors have shown how to break the AES cryptographic algorithm with side channel attacks, specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present a practical timing attack on NoC that improves Prime+Probe technique. Our attack targets the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore, we evaluate a secure enhanced NoC...
The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration between devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets...
The exigency for heterogeneous many-core systems has brought an exponential growth in the complexity of their interconnections. In this manner, other Network-on-Chip (NoC) alternatives are being sought to attend the requirements in terms of power consumption and performance. Nevertheless, several of these proposals present very complex architectures, with virtual channels, tables and extra controls...
Multi-Processors Systems-on-Chip (MPSoCs) are demanding for high performance, low power and high density, and therefore, three-dimensional integrated circuits (3DIC) emerge as a solution to integrate these systems. In order to appropriately interconnect the layers of these systems in terms of flexibility and scalability, a Network-on-Chip (NoC) is typically employed. In this paper, we argue about...
Networks-on-chip has been seen as an interconnect solution for complex systems. However, performance and energy issues still represent limiting factors for Multi-Processors System-on-Chip (MPSoC). Complex router architectures can be prohibitive for the embedded domain, once they dissipate too much power and energy. In this paper we propose a low power hierarchical network topology with GALS interfaces,...
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