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A compact-size and high-isolation microwave diplexer for system-in-a-package has been proposed. By employing the folded stepped-impedance resonators (SIRs), the overall circuit size can be significant reduced. For demonstration, a diplexer operating at 0.5 GHz and 0.86 GHz with third-order Chebyshev bandpass response has been designed and fabricated with microstrip technology. As a result, the diplexer...
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-rate-distortion optimization...
We design, implement, and evaluate an H.264/SVC decoder and an HTTP video streaming client on multi-core mobile devices. The decoder employs multiple decoder threads to leverage the multi-core CPUs, and the streaming server/client support adaptive HTTP video streaming. To evaluate the decoder performance, we conduct experiments using real H.264/SVC videos on a tablet and a smart phone running Android...
We consider the decision engine of mobile cloud offloading systems, which decides whether to offload a given method to the cloud servers. We design, implement, and evaluate a context-aware decision algorithm, called CADA, to optimize the performance of the mobile devices with various optimization criteria, including short response time and low energy consumption. The CADA algorithm can work with various...
A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18mum CMOS (Tsu-Ming Liu, 2006). The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz...
An MPEG-2 and H.264/AVC decoder occupies 3.9 times 3.9mm2 in 0.18mum 1P6M CMOS. To improve integration efficiency and transmission bandwidth, a scalable pipeline and prediction circuit is employed. The decoder performs real-time MPEG-2 and H.264/AVC QCIF at 15frames/s video decoding, dissipating 108muW and 125muW, respectively, at 1V with a clock frequency of 1.15MHz
A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865-muW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4times4 sub-block level pipelining that achieves...
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