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Recent development of Electron Backscattering Diffraction (EBSD) technique has advanced to allow users to perform Transmission Kikuchi diffraction (TKD), and also known as transmission-EBSD (t-EBSD) with the existing conventional EBSD detector, and field emission scanning electron microscope (FESEM). More importantly, this technique has been known for the significant improvement in spatial resolution...
Microstructure analysis plays an important role in the reliability study of copper Through-Silicon Vias (TSVs). While conventional 2-dimensional (2D) Electron Back-Scatter Diffraction (EBSD) is a useful technique, 3-dimensional (3D) EBSD characterization provides a more accurate picture of the TSV microstructure. Information that is missing in 2D observations, such as grain shape and volume, can be...
Copper Through-Silicon Via (Cu TSV) is becoming a key technology for three dimensional (3D) packaging and 3D integrated circuit (IC) applications. The microstructure of the Cu TSV is important as it not only affects the electrical properties, but ma y play a role in its reliability such as protrusion. In this study, physical vapor deposition (PVD) and electroplated (ECP) Cu TSV microstructure evolution...
In wirebonding, high stresses applied onto the pad during the ultrasonic bonding can result in pad damage, silicon cratering and aluminium splash — all of which ultimately result in poor joint quality. Cracking in the Cu/low-k and Cu/ultra low-k layers beneath the pad (also a result of high applied stresses) is a common issue with wirebonding. As a result of these failures in the substrate and the...
The use of copper wire for wire bonding integrated circuits (ICs) has increased significantly in recent years, driven mainly by the dramatic increase in the cost of gold. The technical advantages and limitations, particularly with respect to reliability, of copper for wire bonding, compared with gold, have been widely reported. This paper describes reliability studies comparing on copper, palladium...
Two test chips have been designed to determine the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). One of the chips uses via-middle technology while the other uses via-last technology. Both chips are fabricated in a commercial foundry using a 65 nm CMOS process. Both chips contain test structures designed to measure performance of transistors and other active...
A test chip has been designed and fabricated to validate the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). The test chip contains test structures designed to measure the electromigration performance of TSVs and microbump, thermal performance, stress in the chip as a result of thinning and die stacking, and corrosion related to moisture ingress. The structures...
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